mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-01 18:48:10 +02:00
Fixed conflicts in delay and elmore modules on merge with dev.
This commit is contained in:
Hunter Nichols
+13
-12
@@ -120,8 +120,9 @@ class sram_1bank(sram_base):
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port = 0
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# The row address bits are placed above the control logic aligned on the right.
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x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width
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# It is above the control logic but below the top of the bitcell array
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y_offset = max(self.control_logic_insts[port].uy(), self.bank.predecoder_height)
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# It is above the control logic and the predecoder array
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y_offset = max(self.control_logic_insts[port].uy(), self.bank.predecoder_top)
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self.row_addr_pos[port] = vector(x_offset, y_offset)
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self.row_addr_dff_insts[port].place(self.row_addr_pos[port])
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@@ -130,7 +131,7 @@ class sram_1bank(sram_base):
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# The row address bits are placed above the control logic aligned on the left.
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x_offset = self.control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width
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# If it can be placed above the predecoder and below the control logic, do it
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y_offset = self.bank.bank_array_ll.y
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y_offset = self.bank.predecoder_bottom
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self.row_addr_pos[port] = vector(x_offset, y_offset)
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self.row_addr_dff_insts[port].place(self.row_addr_pos[port], mirror="XY")
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@@ -419,11 +420,11 @@ class sram_1bank(sram_base):
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if len(route_map) > 0:
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# The write masks will have blockages on M1
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if self.num_wmasks > 0 and port in self.write_ports:
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layer_stack = self.m3_stack
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else:
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layer_stack = self.m1_stack
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# if self.num_wmasks > 0 and port in self.write_ports:
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# layer_stack = self.m3_stack
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# else:
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# layer_stack = self.m1_stack
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layer_stack = self.m3_stack
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if port == 0:
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offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
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- self.data_bus_size[port] + 2 * self.m3_pitch)
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@@ -527,13 +528,13 @@ class sram_1bank(sram_base):
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# Only input (besides pins) is the replica bitline
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src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
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dest_pin = self.bank_inst.get_pin("rbl_bl_{0}_{0}".format(port))
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self.add_wire(self.m2_stack[::-1],
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self.add_wire(self.m3_stack,
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[src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()])
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self.add_via_stack_center(from_layer=src_pin.layer,
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to_layer="m2",
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to_layer="m4",
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offset=src_pin.center())
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self.add_via_stack_center(from_layer=dest_pin.layer,
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to_layer="m2",
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to_layer="m3",
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offset=dest_pin.center())
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def route_row_addr_dff(self):
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@@ -612,7 +613,7 @@ class sram_1bank(sram_base):
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# Sanity check in case it was forgotten
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if inst_name.find("x") != 0:
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inst_name = "x" + inst_name
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return self.bank_inst.mod.get_cell_name(inst_name + ".x" + self.bank_inst.name, row, col)
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return self.bank_inst.mod.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bank_inst.name, row, col)
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def get_bank_num(self, inst_name, row, col):
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return 0
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+89
-32
@@ -225,11 +225,7 @@ class sram_base(design, verilog, lef):
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for pin_name in ["vdd", "gnd"]:
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for inst in self.insts:
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self.copy_power_pins(inst, pin_name)
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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return
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try:
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from tech import power_grid
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grid_stack = power_grid
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@@ -238,38 +234,99 @@ class sram_base(design, verilog, lef):
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# Route a M3/M4 grid
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grid_stack = self.m3_stack
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if OPTS.route_supplies == "grid":
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from supply_grid_router import supply_grid_router as router
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elif OPTS.route_supplies:
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from supply_tree_router import supply_tree_router as router
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# lowest_coord = self.find_lowest_coords()
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# highest_coord = self.find_highest_coords()
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rtr=router(grid_stack, self)
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# # Add two rails to the side
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# if OPTS.route_supplies == "side":
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# supply_pins = {}
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# # Find the lowest leftest pin for vdd and gnd
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# for (pin_name, pin_index) in [("vdd", 0), ("gnd", 1)]:
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# pin_width = 8 * getattr(self, "{}_width".format(grid_stack[2]))
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# pin_space = 2 * getattr(self, "{}_space".format(grid_stack[2]))
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# supply_pitch = pin_width + pin_space
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# # Add side power rails on left from bottom to top
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# # These have a temporary name and will be connected later.
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# # They are here to reserve space now and ensure other pins go beyond
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# # their perimeter.
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# supply_height = highest_coord.y - lowest_coord.y
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# supply_pins[pin_name] = self.add_layout_pin(text=pin_name,
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# layer=grid_stack[2],
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# offset=lowest_coord + vector(pin_index * supply_pitch, 0),
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# width=pin_width,
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# height=supply_height)
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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return
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elif OPTS.route_supplies == "grid":
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from supply_grid_router import supply_grid_router as router
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else:
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from supply_tree_router import supply_tree_router as router
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rtr=router(grid_stack, self, side_pin=(OPTS.route_supplies == "side"))
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rtr.route()
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# Find the lowest leftest pin for vdd and gnd
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for pin_name in ["vdd", "gnd"]:
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# Copy the pin shape(s) to rectangles
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for pin in self.get_pins(pin_name):
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if OPTS.route_supplies == "side":
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# Find the lowest leftest pin for vdd and gnd
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for pin_name in ["vdd", "gnd"]:
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# Copy the pin shape(s) to rectangles
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for pin in self.get_pins(pin_name):
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self.add_rect(pin.layer,
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pin.ll(),
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pin.width(),
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pin.height())
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# Remove the pin shape(s)
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self.remove_layout_pin(pin_name)
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# Get the lowest, leftest pin
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pin = rtr.get_ll_pin(pin_name)
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self.add_layout_pin(pin_name,
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pin.layer,
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pin.ll(),
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pin.width(),
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pin.height())
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elif OPTS.route_supplies:
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# Update these as we may have routed outside the region (perimeter pins)
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lowest_coord = self.find_lowest_coords()
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# Find the lowest leftest pin for vdd and gnd
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for pin_name in ["vdd", "gnd"]:
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# Copy the pin shape(s) to rectangles
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for pin in self.get_pins(pin_name):
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self.add_rect(pin.layer,
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pin.ll(),
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pin.width(),
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pin.height())
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# Remove the pin shape(s)
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self.remove_layout_pin(pin_name)
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# Get the lowest, leftest pin
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pin = rtr.get_ll_pin(pin_name)
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pin_width = 2 * getattr(self, "{}_width".format(pin.layer))
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# Add it as an IO pin to the perimeter
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route_width = pin.rx() - lowest_coord.x
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pin_offset = vector(lowest_coord.x, pin.by())
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self.add_rect(pin.layer,
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pin.ll(),
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pin.width(),
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pin_offset,
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route_width,
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pin.height())
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# Remove the pin shape(s)
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self.remove_layout_pin(pin_name)
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# Get the lowest, leftest pin
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pin = rtr.get_ll_pin(pin_name)
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# Add it as an IO pin to the perimeter
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lowest_coord = self.find_lowest_coords()
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pin_width = pin.rx() - lowest_coord.x
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pin_offset = vector(lowest_coord.x, pin.by())
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self.add_layout_pin(pin_name,
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pin.layer,
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pin_offset,
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pin_width,
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pin.height())
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self.add_layout_pin(pin_name,
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pin.layer,
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pin_offset,
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pin_width,
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pin.height())
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else:
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# Grid is left with many top level pins
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pass
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def route_escape_pins(self):
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"""
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@@ -314,7 +371,7 @@ class sram_base(design, verilog, lef):
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from signal_escape_router import signal_escape_router as router
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rtr=router(layers=self.m3_stack,
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design=self,
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margin=4 * self.m3_pitch)
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margin=8 * self.m3_pitch)
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rtr.escape_route(pins_to_route)
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def compute_bus_sizes(self):
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