mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-30 01:48:33 +02:00
Fixed conflicts in delay and elmore modules on merge with dev.
This commit is contained in:
Hunter Nichols
@@ -69,7 +69,7 @@ class delay(simulation):
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for meas in meas_list:
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name = meas.name.lower()
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debug.check(name not in name_set, ("SPICE measurements must have unique names. "
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"Duplicate name={}").format(name))
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"Duplicate name={0}").format(name))
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name_set.add(name)
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def create_read_port_measurement_objects(self):
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@@ -77,7 +77,7 @@ class delay(simulation):
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self.read_lib_meas = []
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self.clk_frmt = "clk{0}" # Unformatted clock name
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targ_name = "{0}{1}_{2}".format(self.dout_name, "{}", self.probe_data) # Empty values are the port and probe data bit
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targ_name = "{0}{{}}_{1}".format(self.dout_name, self.probe_data) # Empty values are the port and probe data bit
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self.delay_meas = []
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self.delay_meas.append(delay_measure("delay_lh", self.clk_frmt, targ_name, "RISE", "RISE", measure_scale=1e9))
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self.delay_meas[-1].meta_str = sram_op.READ_ONE # Used to index time delay values when measurements written to spice file.
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@@ -166,7 +166,7 @@ class delay(simulation):
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self.dout_volt_meas = []
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for meas in self.delay_meas:
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# Output voltage measures
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self.dout_volt_meas.append(voltage_at_measure("v_{}".format(meas.name),
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self.dout_volt_meas.append(voltage_at_measure("v_{0}".format(meas.name),
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meas.targ_name_no_port))
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self.dout_volt_meas[-1].meta_str = meas.meta_str
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@@ -186,7 +186,7 @@ class delay(simulation):
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self.read_bit_meas = {bit_polarity.NONINVERTING: [], bit_polarity.INVERTING: []}
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meas_cycles = (sram_op.READ_ZERO, sram_op.READ_ONE)
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for cycle in meas_cycles:
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meas_tag = "a{}_b{}_{}".format(self.probe_address, self.probe_data, cycle.name)
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meas_tag = "a{0}_b{1}_{2}".format(self.probe_address, self.probe_data, cycle.name)
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single_bit_meas = self.get_bit_measures(meas_tag, self.probe_address, self.probe_data)
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for polarity, meas in single_bit_meas.items():
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meas.meta_str = cycle
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@@ -200,7 +200,7 @@ class delay(simulation):
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self.write_bit_meas = {bit_polarity.NONINVERTING: [], bit_polarity.INVERTING: []}
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meas_cycles = (sram_op.WRITE_ZERO, sram_op.WRITE_ONE)
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for cycle in meas_cycles:
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meas_tag = "a{}_b{}_{}".format(self.probe_address, self.probe_data, cycle.name)
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meas_tag = "a{0}_b{1}_{2}".format(self.probe_address, self.probe_data, cycle.name)
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single_bit_meas = self.get_bit_measures(meas_tag, self.probe_address, self.probe_data)
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for polarity, meas in single_bit_meas.items():
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meas.meta_str = cycle
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@@ -219,20 +219,20 @@ class delay(simulation):
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(cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, bit_row, bit_col)
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storage_names = cell_inst.mod.get_storage_net_names()
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debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes"
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"supported for characterization. Storage nets={}").format(storage_names))
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"supported for characterization. Storage nets={0}").format(storage_names))
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if OPTS.use_pex and OPTS.pex_exe[0] != "calibre":
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bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col)
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q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col)
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qbar_name = "bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col)
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else:
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q_name = cell_name + '.' + str(storage_names[0])
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qbar_name = cell_name + '.' + str(storage_names[1])
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q_name = cell_name + OPTS.hier_seperator + str(storage_names[0])
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qbar_name = cell_name + OPTS.hier_seperator + str(storage_names[1])
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# Bit measures, measurements times to be defined later. The measurement names must be unique
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# but they is enforced externally. {} added to names to differentiate between ports allow the
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# measurements are independent of the ports
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q_meas = voltage_at_measure("v_q_{}".format(meas_tag), q_name)
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qbar_meas = voltage_at_measure("v_qbar_{}".format(meas_tag), qbar_name)
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q_meas = voltage_at_measure("v_q_{0}".format(meas_tag), q_name)
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qbar_meas = voltage_at_measure("v_qbar_{0}".format(meas_tag), qbar_name)
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return {bit_polarity.NONINVERTING: q_meas, bit_polarity.INVERTING: qbar_meas}
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@@ -242,15 +242,15 @@ class delay(simulation):
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# FIXME: There should be a default_read_port variable in this case, pathing is done with this
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# but is never mentioned otherwise
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port = self.read_ports[0]
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sen_and_port = self.sen_name+str(port)
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sen_and_port = self.sen_name + str(port)
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bl_and_port = self.bl_name.format(port) # bl_name contains a '{}' for the port
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# Isolate the s_en and bitline paths
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debug.info(1, "self.bl_name = {}".format(self.bl_name))
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debug.info(1, "self.graph.all_paths = {}".format(self.graph.all_paths))
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debug.info(1, "self.bl_name = {0}".format(self.bl_name))
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debug.info(1, "self.graph.all_paths = {0}".format(self.graph.all_paths))
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sen_paths = [path for path in self.graph.all_paths if sen_and_port in path]
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bl_paths = [path for path in self.graph.all_paths if bl_and_port in path]
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debug.check(len(sen_paths)==1, 'Found {} paths which contain the s_en net.'.format(len(sen_paths)))
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debug.check(len(bl_paths)==1, 'Found {} paths which contain the bitline net.'.format(len(bl_paths)))
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debug.check(len(sen_paths)==1, 'Found {0} paths which contain the s_en net.'.format(len(sen_paths)))
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debug.check(len(bl_paths)==1, 'Found {0} paths which contain the bitline net.'.format(len(bl_paths)))
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sen_path = sen_paths[0]
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bitline_path = bl_paths[0]
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@@ -286,11 +286,11 @@ class delay(simulation):
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# Create the measurements
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path_meas = []
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for i in range(len(path)-1):
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cur_net, next_net = path[i], path[i+1]
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cur_dir, next_dir = path_dirs[i], path_dirs[i+1]
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meas_name = "delay_{}_to_{}".format(cur_net, next_net)
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if i+1 != len(path)-1:
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for i in range(len(path) - 1):
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cur_net, next_net = path[i], path[i + 1]
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cur_dir, next_dir = path_dirs[i], path_dirs[i + 1]
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meas_name = "delay_{0}_to_{1}".format(cur_net, next_net)
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if i + 1 != len(path) - 1:
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path_meas.append(delay_measure(meas_name, cur_net, next_net, cur_dir, next_dir, measure_scale=1e9, has_port=False))
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else: # Make the last measurement always measure on FALL because is a read 0
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path_meas.append(delay_measure(meas_name, cur_net, next_net, cur_dir, "FALL", measure_scale=1e9, has_port=False))
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@@ -309,13 +309,13 @@ class delay(simulation):
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# Convert to booleans based on function of modules (inverting/non-inverting)
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mod_type_bools = [mod.is_non_inverting() for mod in edge_mods]
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#FIXME: obtuse hack to differentiate s_en input from bitline in sense amps
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# FIXME: obtuse hack to differentiate s_en input from bitline in sense amps
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if self.sen_name in path:
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# Force the sense amp to be inverting for s_en->DOUT.
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# bitline->DOUT is non-inverting, but the module cannot differentiate inputs.
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s_en_index = path.index(self.sen_name)
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mod_type_bools[s_en_index] = False
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debug.info(2,'Forcing sen->dout to be inverting.')
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debug.info(2, 'Forcing sen->dout to be inverting.')
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# Use these to determine direction list assuming delay start on neg. edge of clock (FALL)
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# Also, use shorthand that 'FALL' == False, 'RISE' == True to simplify logic
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@@ -493,7 +493,7 @@ class delay(simulation):
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elif meas_type is voltage_at_measure:
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variant_tuple = self.get_volt_at_measure_variants(port, measure_obj)
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else:
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debug.error("Input function not defined for measurement type={}".format(meas_type))
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debug.error("Input function not defined for measurement type={0}".format(meas_type))
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# Removes port input from any object which does not use it. This shorthand only works if
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# the measurement has port as the last input. Could be implemented by measurement type or
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# remove entirely from measurement classes.
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@@ -515,7 +515,7 @@ class delay(simulation):
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elif delay_obj.meta_str == sram_op.READ_ONE:
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meas_cycle_delay = self.cycle_times[self.measure_cycles[port][delay_obj.meta_str]]
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else:
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debug.error("Unrecognized delay Index={}".format(delay_obj.meta_str),1)
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debug.error("Unrecognized delay Index={0}".format(delay_obj.meta_str), 1)
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# These measurements have there time further delayed to the neg. edge of the clock.
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if delay_obj.meta_add_delay:
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@@ -587,20 +587,20 @@ class delay(simulation):
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# Output some comments to aid where cycles start and
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# what is happening
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for comment in self.cycle_comments:
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self.sf.write("* {}\n".format(comment))
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self.sf.write("* {0}\n".format(comment))
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self.sf.write("\n")
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for read_port in self.targ_read_ports:
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self.sf.write("* Read ports {}\n".format(read_port))
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self.sf.write("* Read ports {0}\n".format(read_port))
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self.write_delay_measures_read_port(read_port)
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for write_port in self.targ_write_ports:
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self.sf.write("* Write ports {}\n".format(write_port))
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self.sf.write("* Write ports {0}\n".format(write_port))
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self.write_delay_measures_write_port(write_port)
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def load_pex_net(self, net: str):
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from subprocess import check_output, CalledProcessError
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prefix = (self.sram_instance_name + ".").lower()
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prefix = (self.sram_instance_name + OPTS.hier_seperator).lower()
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if not net.lower().startswith(prefix) or not OPTS.use_pex or not OPTS.calibre_pex:
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return net
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original_net = net
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@@ -640,26 +640,41 @@ class delay(simulation):
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col = self.bitline_column
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row = self.wordline_row
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for port in set(self.targ_read_ports + self.targ_write_ports):
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probe_nets.add("WEB{}".format(port))
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probe_nets.add("{}.w_en{}".format(self.sram_instance_name, port))
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probe_nets.add("{0}.Xbank0.Xport_data{1}.Xwrite_driver_array{1}.Xwrite_driver{2}.en_bar".format(
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self.sram_instance_name, port, self.bitline_column))
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probe_nets.add("{}.Xbank0.br_{}_{}".format(self.sram_instance_name, port,
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self.bitline_column))
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probe_nets.add("WEB{0}".format(port))
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probe_nets.add("{0}{2}w_en{1}".format(self.sram_instance_name, port, OPTS.hier_seperator))
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probe_nets.add("{0}{3}Xbank0{3}Xport_data{1}{3}Xwrite_driver_array{1}{3}Xwrite_driver{2}{3}en_bar".format(self.sram_instance_name,
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port,
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self.bitline_column,
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OPTS.hier_seperator))
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probe_nets.add("{0}{3}Xbank0{3}br_{1}_{2}".format(self.sram_instance_name,
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port,
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self.bitline_column,
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OPTS.hier_seperator))
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if not OPTS.use_pex:
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continue
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probe_nets.add(
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"{0}.vdd_Xbank0_Xbitcell_array_xbitcell_array_xbit_r{1}_c{2}".format(sram_name, row, col - 1))
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"{0}{3}vdd_Xbank0_Xbitcell_array_xbitcell_array_xbit_r{1}_c{2}".format(sram_name,
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row,
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col - 1,
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OPTS.hier_seperator))
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probe_nets.add(
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"{0}.p_en_bar{1}_Xbank0_Xport_data{1}_Xprecharge_array{1}_Xpre_column_{2}".format(sram_name, port, col))
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"{0}{3}p_en_bar{1}_Xbank0_Xport_data{1}_Xprecharge_array{1}_Xpre_column_{2}".format(sram_name,
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port,
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col,
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OPTS.hier_seperator))
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probe_nets.add(
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"{0}.vdd_Xbank0_Xport_data{1}_Xprecharge_array{1}_xpre_column_{2}".format(sram_name, port, col))
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probe_nets.add("{0}.vdd_Xbank0_Xport_data{1}_Xwrite_driver_array{1}_xwrite_driver{2}".format(sram_name,
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port, col))
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"{0}{3}vdd_Xbank0_Xport_data{1}_Xprecharge_array{1}_xpre_column_{2}".format(sram_name,
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port,
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col,
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OPTS.hier_seperator))
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probe_nets.add("{0}{3}vdd_Xbank0_Xport_data{1}_Xwrite_driver_array{1}_xwrite_driver{2}".format(sram_name,
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port,
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col,
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OPTS.hier_seperator))
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probe_nets.update(self.measurement_nets)
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for net in probe_nets:
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debug.info(2, "Probe: {}".format(net))
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self.sf.write(".plot V({}) \n".format(self.load_pex_net(net)))
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debug.info(2, "Probe: {0}".format(net))
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self.sf.write(".plot V({0}) \n".format(self.load_pex_net(net)))
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def write_power_measures(self):
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"""
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@@ -778,7 +793,7 @@ class delay(simulation):
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if not self.check_bit_measures(self.write_bit_meas, port):
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return(False, {})
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debug.info(2, "Checking write values for port {}".format(port))
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debug.info(2, "Checking write values for port {0}".format(port))
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write_port_dict = {}
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for measure in self.write_lib_meas:
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write_port_dict[measure.name] = measure.retrieve_measure(port=port)
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@@ -792,7 +807,7 @@ class delay(simulation):
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if not self.check_bit_measures(self.read_bit_meas, port):
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return(False, {})
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debug.info(2, "Checking read delay values for port {}".format(port))
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debug.info(2, "Checking read delay values for port {0}".format(port))
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# Check sen timing, then bitlines, then general measurements.
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if not self.check_sen_measure(port):
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return (False, {})
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@@ -821,7 +836,7 @@ class delay(simulation):
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"""Checks that the sen occurred within a half-period"""
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sen_val = self.sen_meas.retrieve_measure(port=port)
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debug.info(2, "s_en delay={}ns".format(sen_val))
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debug.info(2, "s_en delay={0}ns".format(sen_val))
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if self.sen_meas.meta_add_delay:
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max_delay = self.period / 2
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else:
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@@ -843,22 +858,22 @@ class delay(simulation):
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elif self.br_name == meas.targ_name_no_port:
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br_vals[meas.meta_str] = val
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debug.info(2, "{}={}".format(meas.name, val))
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debug.info(2, "{0}={1}".format(meas.name, val))
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dout_success = True
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bl_success = False
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for meas in self.dout_volt_meas:
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val = meas.retrieve_measure(port=port)
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debug.info(2, "{}={}".format(meas.name, val))
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debug.info(2, "{0}={1}".format(meas.name, val))
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debug.check(type(val)==float, "Error retrieving numeric measurement: {0} {1}".format(meas.name, val))
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if meas.meta_str == sram_op.READ_ONE and val < self.vdd_voltage * 0.1:
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dout_success = False
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debug.info(1, "Debug measurement failed. Value {}V was read on read 1 cycle.".format(val))
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debug.info(1, "Debug measurement failed. Value {0}V was read on read 1 cycle.".format(val))
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bl_success = self.check_bitline_meas(bl_vals[sram_op.READ_ONE], br_vals[sram_op.READ_ONE])
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elif meas.meta_str == sram_op.READ_ZERO and val > self.vdd_voltage * 0.9:
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dout_success = False
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debug.info(1, "Debug measurement failed. Value {}V was read on read 0 cycle.".format(val))
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debug.info(1, "Debug measurement failed. Value {0}V was read on read 0 cycle.".format(val))
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bl_success = self.check_bitline_meas(br_vals[sram_op.READ_ONE], bl_vals[sram_op.READ_ONE])
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# If the bitlines have a correct value while the output does not then that is a
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@@ -877,7 +892,7 @@ class delay(simulation):
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for polarity, meas_list in bit_measures.items():
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for meas in meas_list:
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val = meas.retrieve_measure(port=port)
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debug.info(2, "{}={}".format(meas.name, val))
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debug.info(2, "{0}={1}".format(meas.name, val))
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if type(val) != float:
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continue
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meas_cycle = meas.meta_str
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@@ -896,8 +911,8 @@ class delay(simulation):
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success = val < self.vdd_voltage / 2
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if not success:
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debug.info(1, ("Wrong value detected on probe bit during read/write cycle. "
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"Check writes and control logic for bugs.\n measure={}, op={}, "
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"bit_storage={}, V(bit)={}").format(meas.name, meas_cycle.name, polarity.name, val))
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"Check writes and control logic for bugs.\n measure={0}, op={1}, "
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"bit_storage={2}, V(bit)={3}").format(meas.name, meas_cycle.name, polarity.name, val))
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return success
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@@ -912,7 +927,7 @@ class delay(simulation):
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min_dicharge = v_discharged_bl < self.vdd_voltage * 0.9
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min_diff = (v_charged_bl - v_discharged_bl) > self.vdd_voltage * 0.1
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debug.info(1, "min_dicharge={}, min_diff={}".format(min_dicharge, min_diff))
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debug.info(1, "min_dicharge={0}, min_diff={1}".format(min_dicharge, min_diff))
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return (min_dicharge and min_diff)
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def check_path_measures(self):
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@@ -921,11 +936,11 @@ class delay(simulation):
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# Get and set measurement, no error checking done other than prints.
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debug.info(2, "Checking measures in Delay Path")
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value_dict = {}
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for meas in self.sen_path_meas+self.bl_path_meas:
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for meas in self.sen_path_meas + self.bl_path_meas:
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val = meas.retrieve_measure()
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debug.info(2, '{}={}'.format(meas.name, val))
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if type(val) != float or val > self.period/2:
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debug.info(1,'Failed measurement:{}={}'.format(meas.name, val))
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||||
debug.info(2, '{0}={1}'.format(meas.name, val))
|
||||
if type(val) != float or val > self.period / 2:
|
||||
debug.info(1, 'Failed measurement:{}={}'.format(meas.name, val))
|
||||
value_dict[meas.name] = val
|
||||
#debug.info(0, "value_dict={}".format(value_dict))
|
||||
return value_dict
|
||||
@@ -1100,14 +1115,14 @@ class delay(simulation):
|
||||
|
||||
# Set up to trim the netlist here if that is enabled
|
||||
if OPTS.trim_netlist:
|
||||
self.trim_sp_file = "{}trimmed.sp".format(OPTS.openram_temp)
|
||||
self.trim_sp_file = "{0}trimmed.sp".format(OPTS.openram_temp)
|
||||
self.sram.sp_write(self.trim_sp_file, lvs=False, trim=True)
|
||||
else:
|
||||
# The non-reduced netlist file when it is disabled
|
||||
self.trim_sp_file = "{}sram.sp".format(OPTS.openram_temp)
|
||||
self.trim_sp_file = "{0}sram.sp".format(OPTS.openram_temp)
|
||||
|
||||
# The non-reduced netlist file for power simulation
|
||||
self.sim_sp_file = "{}sram.sp".format(OPTS.openram_temp)
|
||||
self.sim_sp_file = "{0}sram.sp".format(OPTS.openram_temp)
|
||||
# Make a copy in temp for debugging
|
||||
shutil.copy(self.sp_file, self.sim_sp_file)
|
||||
|
||||
@@ -1194,6 +1209,7 @@ class delay(simulation):
|
||||
for mname, value in delay_results[port].items():
|
||||
if "power" in mname:
|
||||
# Subtract partial array leakage and add full array leakage for the power measures
|
||||
debug.info(1, "Adding leakage offset to {0} {1} + {2} = {3}".format(mname, value, leakage_offset, value + leakage_offset))
|
||||
measure_data[port][mname].append(value + leakage_offset)
|
||||
else:
|
||||
measure_data[port][mname].append(value)
|
||||
@@ -1246,13 +1262,13 @@ class delay(simulation):
|
||||
if self.t_current == 0:
|
||||
self.add_noop_all_ports("Idle cycle (no positive clock edge)")
|
||||
|
||||
self.add_write("W data 1 address {}".format(inverse_address),
|
||||
self.add_write("W data 1 address {0}".format(inverse_address),
|
||||
inverse_address,
|
||||
data_ones,
|
||||
wmask_ones,
|
||||
write_port)
|
||||
|
||||
self.add_write("W data 0 address {} to write value".format(self.probe_address),
|
||||
self.add_write("W data 0 address {0} to write value".format(self.probe_address),
|
||||
self.probe_address,
|
||||
data_zeros,
|
||||
wmask_ones,
|
||||
@@ -1263,11 +1279,11 @@ class delay(simulation):
|
||||
self.measure_cycles[write_port]["disabled_write0"] = len(self.cycle_times) - 1
|
||||
|
||||
# This also ensures we will have a H->L transition on the next read
|
||||
self.add_read("R data 1 address {} to set dout caps".format(inverse_address),
|
||||
self.add_read("R data 1 address {0} to set dout caps".format(inverse_address),
|
||||
inverse_address,
|
||||
read_port)
|
||||
|
||||
self.add_read("R data 0 address {} to check W0 worked".format(self.probe_address),
|
||||
self.add_read("R data 0 address {0} to check W0 worked".format(self.probe_address),
|
||||
self.probe_address,
|
||||
read_port)
|
||||
self.measure_cycles[read_port][sram_op.READ_ZERO] = len(self.cycle_times) - 1
|
||||
@@ -1277,7 +1293,7 @@ class delay(simulation):
|
||||
|
||||
self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)")
|
||||
|
||||
self.add_write("W data 1 address {} to write value".format(self.probe_address),
|
||||
self.add_write("W data 1 address {0} to write value".format(self.probe_address),
|
||||
self.probe_address,
|
||||
data_ones,
|
||||
wmask_ones,
|
||||
@@ -1287,7 +1303,7 @@ class delay(simulation):
|
||||
self.add_noop_clock_one_port(write_port)
|
||||
self.measure_cycles[write_port]["disabled_write1"] = len(self.cycle_times) - 1
|
||||
|
||||
self.add_write("W data 0 address {} to clear din caps".format(inverse_address),
|
||||
self.add_write("W data 0 address {0} to clear din caps".format(inverse_address),
|
||||
inverse_address,
|
||||
data_zeros,
|
||||
wmask_ones,
|
||||
@@ -1297,11 +1313,11 @@ class delay(simulation):
|
||||
self.measure_cycles[read_port]["disabled_read1"] = len(self.cycle_times) - 1
|
||||
|
||||
# This also ensures we will have a L->H transition on the next read
|
||||
self.add_read("R data 0 address {} to clear dout caps".format(inverse_address),
|
||||
self.add_read("R data 0 address {0} to clear dout caps".format(inverse_address),
|
||||
inverse_address,
|
||||
read_port)
|
||||
|
||||
self.add_read("R data 1 address {} to check W1 worked".format(self.probe_address),
|
||||
self.add_read("R data 1 address {0} to check W1 worked".format(self.probe_address),
|
||||
self.probe_address,
|
||||
read_port)
|
||||
self.measure_cycles[read_port][sram_op.READ_ONE] = len(self.cycle_times) - 1
|
||||
|
||||
Reference in New Issue
Block a user