mirror of https://github.com/VLSIDA/OpenRAM.git
Remove success initialization
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@ -653,7 +653,6 @@ class delay(simulation):
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# Clear any write target ports and set read port
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# Clear any write target ports and set read port
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self.targ_write_ports = [port]
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self.targ_write_ports = [port]
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self.targ_read_ports = [port]
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self.targ_read_ports = [port]
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success = False
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debug.info(1, "Trying feasible period: {0}ns on Port {1}".format(feasible_period, port))
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debug.info(1, "Trying feasible period: {0}ns on Port {1}".format(feasible_period, port))
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self.period = feasible_period
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self.period = feasible_period
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