Merge branch 'dev' into laptop_checkpoint

compiler/base/verilog.py

@@ -55,11 +55,15 @@ class verilog:
                 self.vf.write("    clk{0},csb{0},web{0},".format(port))
                 if self.write_size:
                     self.vf.write("wmask{},".format(port))
+                if self.num_spare_cols > 0:
+                    self.vf.write("spare_wen{0},".format(port))
                 self.vf.write("addr{0},din{0},dout{0}".format(port))
             elif port in self.write_ports:
                 self.vf.write("    clk{0},csb{0},".format(port))
                 if self.write_size:
                     self.vf.write("wmask{},".format(port))
+                if self.num_spare_cols > 0:
+                    self.vf.write("spare_wen{0},".format(port))
                 self.vf.write("addr{0},din{0}".format(port))
             elif port in self.read_ports:
                 self.vf.write("    clk{0},csb{0},addr{0},dout{0}".format(port))
@@ -71,7 +75,7 @@ class verilog:
         if self.write_size:
             self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
             self.vf.write("  parameter NUM_WMASKS = {0} ;\n".format(self.num_wmasks))
-        self.vf.write("  parameter DATA_WIDTH = {0} ;\n".format(self.word_size))
+        self.vf.write("  parameter DATA_WIDTH = {0} ;\n".format(self.word_size + self.num_spare_cols))
         self.vf.write("  parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size))
         self.vf.write("  parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n")
         self.vf.write("  // FIXME: This delay is arbitrary.\n")
@@ -123,6 +127,10 @@ class verilog:
         if port in self.write_ports:
             if self.write_size:
                 self.vf.write("  reg [NUM_WMASKS-1:0]   wmask{0}_reg;\n".format(port))
+            if self.num_spare_cols > 1:
+                self.vf.write("  reg [{1}:0] spare_wen{0}_reg;".format(port, self.num_spare_cols - 1))
+            elif self.num_spare_cols == 1:
+                self.vf.write("  reg spare_wen{0}_reg;\n".format(port))
         self.vf.write("  reg [ADDR_WIDTH-1:0]  addr{0}_reg;\n".format(port))
         if port in self.write_ports:
             self.vf.write("  reg [DATA_WIDTH-1:0]  din{0}_reg;\n".format(port))
@@ -143,6 +151,8 @@ class verilog:
         if port in self.write_ports:
             if self.write_size:
                 self.vf.write("    wmask{0}_reg = wmask{0};\n".format(port))
+            if self.num_spare_cols:
+                self.vf.write("    spare_wen{0}_reg = spare_wen{0};\n".format(port))
             self.vf.write("    addr{0}_reg = addr{0};\n".format(port))
         if port in self.read_ports:
             self.add_write_read_checks(port)
@@ -182,6 +192,11 @@ class verilog:
             self.vf.write("  input  web{0}; // active low write control\n".format(port))
             if self.write_size:
                 self.vf.write("  input [NUM_WMASKS-1:0]   wmask{0}; // write mask\n".format(port))
+            if self.num_spare_cols == 1:
+                self.vf.write("  input           spare_wen{0}; // spare mask\n".format(port))
+            elif self.num_spare_cols > 1:
+                self.vf.write("  input [{1}:0]   spare_wen{0}; // spare mask\n".format(port, self.num_spare_cols-1))
+
         self.vf.write("  input [ADDR_WIDTH-1:0]  addr{0};\n".format(port))
         if port in self.write_ports:
             self.vf.write("  input [DATA_WIDTH-1:0]  din{0};\n".format(port))
@@ -199,29 +214,29 @@ class verilog:
         self.vf.write("  always @ (negedge clk{0})\n".format(port))
         self.vf.write("  begin : MEM_WRITE{0}\n".format(port))
         if port in self.readwrite_ports:
-            if self.write_size:
             self.vf.write("    if ( !csb{0}_reg && !web{0}_reg ) begin\n".format(port))
         else:
-                self.vf.write("    if ( !csb{0}_reg && !web{0}_reg )\n".format(port))
-        else:
-            if self.write_size:
             self.vf.write("    if (!csb{0}_reg) begin\n".format(port))
-            else:
-                self.vf.write("    if (!csb{0}_reg)\n".format(port))
 
         if self.write_size:
-            remainder_bits = self.word_size % self.write_size
             for mask in range(0, self.num_wmasks):
                 lower = mask * self.write_size
-                if (remainder_bits and mask == self.num_wmasks - 1):
-                    upper = lower + remainder_bits - 1
-                else:
                 upper = lower + self.write_size - 1
                 self.vf.write("        if (wmask{0}_reg[{1}])\n".format(port, mask))
                 self.vf.write("                mem[addr{0}_reg][{1}:{2}] = din{0}_reg[{1}:{2}];\n".format(port, upper, lower))
-            self.vf.write("    end\n")
         else:
-            self.vf.write("        mem[addr{0}_reg] = din{0}_reg;\n".format(port))
+            upper = self.word_size - self.num_spare_cols - 1
+            self.vf.write("        mem[addr{0}_reg][{1}:0] = din{0}_reg[{1}:0];\n".format(port, upper))
+
+        if self.num_spare_cols == 1:
+            self.vf.write("        if (spare_wen{0}_reg)\n".format(port))
+            self.vf.write("                mem[addr{0}_reg][{1}] = din{0}_reg[{1}];\n".format(port, self.word_size + num))
+        else:
+            for num in range(self.num_spare_cols):
+                self.vf.write("        if (spare_wen{0}_reg[{1}])\n".format(port, num))
+                self.vf.write("                mem[addr{0}_reg][{1}] = din{0}_reg[{1}];\n".format(port, self.word_size + num))
+
+        self.vf.write("    end\n")
         self.vf.write("  end\n")
 
     def add_read_block(self, port):

compiler/sram/sram_base.py

@@ -84,6 +84,9 @@ class sram_base(design, verilog, lef):
         for port in self.write_ports:
             for bit in range(self.num_wmasks):
                 self.add_pin("wmask{0}[{1}]".format(port, bit), "INPUT")
+            if self.num_spare_cols == 1:
+                self.add_pin("spare_wen{0}".format(port), "INPUT")
+            else:
                 for bit in range(self.num_spare_cols):
                     self.add_pin("spare_wen{0}[{1}]".format(port, bit), "INPUT")
         for port in self.read_ports:
@@ -358,6 +361,9 @@ class sram_base(design, verilog, lef):
                         pins_to_route.append("wmask{0}[{1}]".format(port, bit))
 
             if port in self.write_ports:
+                if self.num_spare_cols == 1:
+                    pins_to_route.append("spare_wen{0}".format(port))
+                else:
                     for bit in range(self.num_spare_cols):
                         pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
 
@@ -562,8 +568,11 @@ class sram_base(design, verilog, lef):
             temp.append("w_en{0}".format(port))
             for bit in range(self.num_wmasks):
                 temp.append("bank_wmask{}[{}]".format(port, bit))
+            if self.num_spare_cols == 1:
+                temp.append("bank_spare_wen{0}".format(port))
+            else:
                 for bit in range(self.num_spare_cols):
-                temp.append("bank_spare_wen{0}[{1}]".format(port, bit))
+                    temp.append("bank_spare_wen{0}_{1}".format(port, bit))
         for port in self.all_ports:
             temp.append("wl_en{0}".format(port))
         temp.extend(self.ext_supplies)
@@ -695,9 +704,13 @@ class sram_base(design, verilog, lef):
             # inputs, outputs/output/bar
             inputs = []
             outputs = []
+            if self.num_spare_cols == 1:
+                inputs.append("spare_wen{}".format(port))
+                outputs.append("bank_spare_wen{}".format(port))
+            else:
                 for bit in range(self.num_spare_cols):
                     inputs.append("spare_wen{}[{}]".format(port, bit))
-                outputs.append("bank_spare_wen{}[{}]".format(port, bit))
+                    outputs.append("bank_spare_wen{}_{}".format(port, bit))
 
             self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
 

compiler/tests/golden/sram_2_16_1_freepdk45.v

@@ -56,8 +56,9 @@ reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
   // Write Operation : When web0 = 0, csb0 = 0
   always @ (negedge clk0)
   begin : MEM_WRITE0
-    if ( !csb0_reg && !web0_reg )
+    if ( !csb0_reg && !web0_reg ) begin
-        mem[addr0_reg] = din0_reg;
+        mem[addr0_reg][1:0] = din0_reg[1:0];
+    end
   end
 
   // Memory Read Block Port 0

compiler/tests/golden/sram_2_16_1_scn4m_subm.v

@@ -56,8 +56,9 @@ reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
   // Write Operation : When web0 = 0, csb0 = 0
   always @ (negedge clk0)
   begin : MEM_WRITE0
-    if ( !csb0_reg && !web0_reg )
+    if ( !csb0_reg && !web0_reg ) begin
-        mem[addr0_reg] = din0_reg;
+        mem[addr0_reg][1:0] = din0_reg[1:0];
+    end
   end
 
   // Memory Read Block Port 0