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Added changes the control logic PWL generation to match changes made in stimuli.

This commit is contained in:
Hunter Nichols 2018-09-25 14:57:49 -07:00
parent 88f2238e03
commit 2e322be7f7
2 changed files with 11 additions and 10 deletions
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19
compiler/characterizer/delay.py
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@ -837,9 +837,10 @@ class delay():
debug.error("Could not add control signals for port {0}. Command {1} not recognized".format(port,op),1) debug.error("Could not add control signals for port {0}. Command {1} not recognized".format(port,op),1)
#Append the values depending on the type of port #Append the values depending on the type of port
self.csb_values[port].append(csb_val) if port in self.read_ports:
self.csb_values[port].append(csb_val)
#If port is in both lists, add rw control signal. Condition indicates its a RW port. #If port is in both lists, add rw control signal. Condition indicates its a RW port.
if port < len(self.web_values): if port in self.write_ports:
self.web_values[port].append(web_val) self.web_values[port].append(web_val)
def add_comment(self, port, comment): def add_comment(self, port, comment):
@ -941,10 +942,10 @@ class delay():
self.measure_cycles = {} self.measure_cycles = {}
# Control signals for ports. These are not the final signals and will likely be changed later. # Control signals for ports. These are not the final signals and will likely be changed later.
#write enable bar for readwrite ports to control read or write #web is the enable for write ports. Dicts used for simplicity as ports are not necessarily incremental.
self.web_values = [[] for i in range(self.readwrite_port_num)] self.web_values = {port:[] for port in self.write_ports}
#csb represents a basic "enable" signal that all ports have. #csb acts as an enable for the read ports.
self.csb_values = [[] for i in range(self.total_port_num)] self.csb_values = {port:[] for port in self.read_ports}
# Address and data values for each address/data bit. A 3d list of size #ports x bits x cycles. # Address and data values for each address/data bit. A 3d list of size #ports x bits x cycles.
self.data_values=[[[] for bit in range(self.word_size)] for port in range(len(self.write_ports))] self.data_values=[[[] for bit in range(self.word_size)] for port in range(len(self.write_ports))]
@ -1036,11 +1037,11 @@ class delay():
def gen_control(self): def gen_control(self):
""" Generates the control signals """ """ Generates the control signals """
for port in range(self.total_port_num): for port in self.read_ports:
self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05) self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05)
for readwrite_port in range(self.readwrite_port_num): for port in self.write_ports:
self.stim.gen_pwl("WEB{0}".format(readwrite_port), self.cycle_times, self.web_values[readwrite_port], self.period, self.slew, 0.05) self.stim.gen_pwl("WEB{0}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05)
def get_empty_measure_data_dict(self): def get_empty_measure_data_dict(self):
"""Make a dict of lists for each type of delay and power measurement to append results to""" """Make a dict of lists for each type of delay and power measurement to append results to"""

2
compiler/example_config_scn4m_subm.py
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@ -16,4 +16,4 @@ bitcell = "pbitcell"
replica_bitcell="replica_pbitcell" replica_bitcell="replica_pbitcell"
num_rw_ports = 1 num_rw_ports = 1
num_r_ports = 0 num_r_ports = 0
num_w_ports = 1 num_w_ports = 0