mirror of https://github.com/VLSIDA/OpenRAM.git
dff array done except for clock net
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parent
0804a1eceb
commit
2d87dcda46
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@ -16,7 +16,7 @@ class dff_array(design.design):
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self.columns = columns
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self.columns = columns
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if name=="":
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if name=="":
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name = "dff_array_c{0}_w{1}".format(columns,word_size)
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name = "dff_array_{0}x{1}".format(rows, columns)
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design.design.__init__(self, name)
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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debug.info(1, "Creating {}".format(self.name))
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@ -49,90 +49,71 @@ class dff_array(design.design):
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self.add_pin("gnd")
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self.add_pin("gnd")
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def create_dff_array(self):
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def create_dff_array(self):
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self.ms_inst={}
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self.dff_insts={}
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for row in range(self.rows):
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for y in range(self.rows):
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for col in range(self.columns):
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for x in range(self.columns):
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name = "Xdff_r{0}_c{1}".format(row,col)
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name = "Xdff_r{0}_c{1}".format(y,x)
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if (row % 2 == 0):
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if (y % 2 == 0):
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base = vector(i*self.ms.width,0)
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base = vector(x*self.ms.width,y*self.ms.height)
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mirror = "R0"
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mirror = "R0"
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else:
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else:
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base = vector((i+1)*self.ms.width,0)
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base = vector(x*self.ms.width,(y+1)*self.ms.height)
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mirror = "MY"
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mirror = "MX"
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self.ms_inst[row,col]=self.add_inst(name=name,
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self.dff_insts[x,y]=self.add_inst(name=name,
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mod=self.ms,
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mod=self.ms,
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offset=base,
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offset=base,
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mirror=mirror)
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mirror=mirror)
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self.connect_inst(["din[{0}][{1}]".format(row,col),
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self.connect_inst(["din[{0}][{1}]".format(x,y),
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"dout[{0}][{1}]".format(row,col),
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"dout[{0}][{1}]".format(x,y),
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"clk",
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"clk",
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"vdd",
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"vdd",
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"gnd"])
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"gnd"])
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def add_layout_pins(self):
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def add_layout_pins(self):
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for i in range(self.word_size):
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for y in range(self.rows):
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# Continous vdd rail along with label.
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vdd_pin=self.dff_insts[0,y].get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll(),
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width=self.width,
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height=drc["minwidth_metal1"])
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for gnd_pin in self.ms_inst[i].get_pins("gnd"):
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# Continous gnd rail along with label.
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if gnd_pin.layer!="metal2":
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gnd_pin=self.dff_insts[0,y].get_pin("gnd")
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continue
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self.add_layout_pin(text="gnd",
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self.add_layout_pin(text="gnd",
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layer="metal1",
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layer="metal2",
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offset=gnd_pin.ll(),
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offset=gnd_pin.ll(),
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width=self.width,
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width=gnd_pin.width(),
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height=drc["minwidth_metal1"])
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height=gnd_pin.height())
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din_pins = self.ms_inst[i].get_pins("din")
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for y in range(self.rows):
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for din_pin in din_pins:
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for x in range(self.columns):
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self.add_layout_pin(text="din[{}]".format(i),
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din_pin = self.dff_insts[x,y].get_pin("d")
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self.add_layout_pin(text="din[{0}][{1}]".format(x,y),
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layer=din_pin.layer,
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layer=din_pin.layer,
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offset=din_pin.ll(),
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offset=din_pin.ll(),
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width=din_pin.width(),
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width=din_pin.width(),
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height=din_pin.height())
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height=din_pin.height())
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dout_pin = self.ms_inst[i].get_pin("dout")
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dout_pin = self.dff_insts[x,y].get_pin("q")
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self.add_layout_pin(text="dout[{}]".format(i),
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self.add_layout_pin(text="dout[{0}][{1}]".format(x,y),
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layer="metal2",
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layer="metal1",
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offset=dout_pin.ll(),
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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width=dout_pin.width(),
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height=dout_pin.height())
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height=dout_pin.height())
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doutbar_pin = self.ms_inst[i].get_pin("dout_bar")
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self.add_layout_pin(text="dout_bar[{}]".format(i),
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layer="metal2",
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offset=doutbar_pin.ll(),
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width=doutbar_pin.width(),
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height=doutbar_pin.height())
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# # Continous clk rail along with label.
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# Continous clk rail along with label.
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# self.add_layout_pin(text="clk",
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self.add_layout_pin(text="clk",
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# layer="metal1",
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layer="metal1",
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# offset=self.dff_insts[0].get_pin("clk").ll().scale(0,1),
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offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1),
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# width=self.width,
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width=self.width,
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# height=drc["minwidth_metal1"])
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height=drc["minwidth_metal1"])
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# Continous vdd rail along with label.
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for vdd_pin in self.ms_inst[i].get_pins("vdd"):
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if vdd_pin.layer!="metal1":
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continue
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll().scale(0,1),
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width=self.width,
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height=drc["minwidth_metal1"])
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# Continous gnd rail along with label.
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for gnd_pin in self.ms_inst[i].get_pins("gnd"):
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if gnd_pin.layer!="metal1":
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continue
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll().scale(0,1),
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width=self.width,
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height=drc["minwidth_metal1"])
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def analytical_delay(self, slew, load=0.0):
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def analytical_delay(self, slew, load=0.0):
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return self.ms.analytical_delay(slew=slew, load=load)
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return self.ms.analytical_delay(slew=slew, load=load)
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@ -21,14 +21,10 @@ class dff_array_test(openram_test):
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import dff_array
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import dff_array
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debug.info(2, "Testing dff_array for columns=8, word_size=8")
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debug.info(2, "Testing dff_array for columns=3, word_size=3")
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a = dff_array.dff_array(columns=8, word_size=8)
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a = dff_array.dff_array(rows=3, columns=3)
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self.local_check(a)
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self.local_check(a)
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debug.info(2, "Testing dff_array for columns=16, word_size=8")
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a = dff_array.dff_array(columns=16, word_size=8)
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self.local_check(a)
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OPTS.check_lvsdrc = True
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OPTS.check_lvsdrc = True
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globals.end_openram()
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globals.end_openram()
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Binary file not shown.
Binary file not shown.
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@ -1,8 +1,10 @@
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magic
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magic
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tech scmos
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tech scmos
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timestamp 1090351116
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timestamp 1518652803
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<< nwell >>
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<< nwell >>
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rect -8 48 104 105
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rect -8 48 104 105
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<< pwell >>
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rect -8 -5 104 48
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<< ntransistor >>
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<< ntransistor >>
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rect 7 6 9 26
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rect 7 6 9 26
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rect 15 6 17 16
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rect 15 6 17 16
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@ -285,9 +287,12 @@ rect 2 30 6 50
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rect 18 20 22 57
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rect 18 20 22 57
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rect 66 44 70 70
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rect 66 44 70 70
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rect 66 20 70 40
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rect 66 20 70 40
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<< m1p >>
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<< m3p >>
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rect 34 43 38 47
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rect -2 0 98 100
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rect 90 43 94 47
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rect 10 33 14 37
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<< labels >>
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<< labels >>
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rlabel metal1 23 100 23 100 5 vdd
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rlabel metal1 38 -1 38 -1 1 gnd
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rlabel metal1 11 34 11 34 1 clk
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rlabel metal1 24 44 24 44 1 d
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rlabel metal1 92 37 92 37 1 q
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<< end >>
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<< end >>
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