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Write size updated in recompute_sizes

This commit is contained in:
Bugra Onal 2022-08-10 15:36:41 -07:00
parent 48fce6485d
commit 2d849aef39
1 changed files with 7 additions and 2 deletions
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9
compiler/modules/sram_config.py
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@ -18,6 +18,7 @@ class sram_config:
self.word_size = word_size self.word_size = word_size
self.num_words = num_words self.num_words = num_words
# Don't add a write mask if it is the same size as the data word # Don't add a write mask if it is the same size as the data word
self.write_size_init = write_size
if write_size: if write_size:
self.write_size = write_size self.write_size = write_size
else: else:
@ -117,6 +118,12 @@ class sram_config:
self.num_rows = self.num_rows_temp + self.num_spare_rows self.num_rows = self.num_rows_temp + self.num_spare_rows
debug.info(1, "Rows: {} Cols: {}".format(self.num_rows_temp, self.num_cols)) debug.info(1, "Rows: {} Cols: {}".format(self.num_rows_temp, self.num_cols))
# Fix the write_size
if self.write_size_init:
self.write_size = self.write_size_init
else:
self.write_size = self.word_size
# Compute the address and bank sizes # Compute the address and bank sizes
self.row_addr_size = ceil(log(self.num_rows, 2)) self.row_addr_size = ceil(log(self.num_rows, 2))
self.col_addr_size = int(log(self.words_per_row, 2)) self.col_addr_size = int(log(self.words_per_row, 2))
@ -127,8 +134,6 @@ class sram_config:
+ " Col addr size: {}".format(self.col_addr_size) + " Col addr size: {}".format(self.col_addr_size)
+ " Bank addr size: {}".format(self.bank_addr_size)) + " Bank addr size: {}".format(self.bank_addr_size))
num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
if num_ports == 1: if num_ports == 1:
if ((self.num_cols + num_ports + self.num_spare_cols) % self.array_col_multiple != 0): if ((self.num_cols + num_ports + self.num_spare_cols) % self.array_col_multiple != 0):