mirror of https://github.com/VLSIDA/OpenRAM.git
Fix netlist_only in sky130
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e49236f8fc
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2b7d89d2c1
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@ -13,10 +13,6 @@ from vector import vector
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from globals import OPTS
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from sram_factory import factory
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if(OPTS.tech_name == "sky130"):
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from tech import nmos_bins, pmos_bins
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class pinv_dec(pinv.pinv):
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"""
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This is another version of pinv but with layout for the decoder.
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@ -129,7 +129,7 @@ class ptx(design.design):
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# be decided in the layout later.
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area_sd = 2.5 * self.poly_width * self.tx_width
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perimeter_sd = 2 * self.poly_width + 2 * self.tx_width
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if OPTS.tech_name == "sky130" and OPTS.lvs_exe[0] == "calibre":
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if OPTS.tech_name == "sky130" and OPTS.lvs_exe and OPTS.lvs_exe[0] == "calibre":
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# sky130 simulation cannot use the mult parameter in simulation
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(self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width)
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main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type],
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@ -150,7 +150,7 @@ class ptx(design.design):
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self.spice_device = main_str + area_str
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self.spice.append("\n* ptx " + self.spice_device)
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if OPTS.tech_name == "sky130" and OPTS.lvs_exe[0] == "calibre":
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if OPTS.tech_name == "sky130" and OPTS.lvs_exe and OPTS.lvs_exe[0] == "calibre":
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# sky130 requires mult parameter too
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self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} mult={1}".format(spice[self.tx_type],
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self.mults,
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@ -57,6 +57,7 @@ class single_level_column_mux(pgate.pgate):
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self.width = self.bitcell.width
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self.height = self.nmos_upper.uy() + self.pin_height
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self.place_ptx()
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self.connect_poly()
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self.add_bitline_pins()
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self.connect_bitlines()
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@ -104,21 +105,28 @@ class single_level_column_mux(pgate.pgate):
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""" Create the two pass gate NMOS transistors to switch the bitlines"""
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# Space it in the center
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nmos_lower_position = self.nmos.active_offset.scale(0, 1) \
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+ vector(0.5 * self.bitcell.width- 0.5 * self.nmos.active_width, 0)
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self.nmos_lower = self.add_inst(name="mux_tx1",
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mod=self.nmos,
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offset=nmos_lower_position)
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mod=self.nmos)
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self.connect_inst(["bl", "sel", "bl_out", "gnd"])
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# This aligns it directly above the other tx with gates abutting
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nmos_upper_position = nmos_lower_position \
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+ vector(0, self.nmos.active_height + max(self.active_space, self.poly_space))
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self.nmos_upper = self.add_inst(name="mux_tx2",
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mod=self.nmos,
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offset=nmos_upper_position)
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mod=self.nmos)
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self.connect_inst(["br", "sel", "br_out", "gnd"])
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def place_ptx(self):
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""" Create the two pass gate NMOS transistors to switch the bitlines"""
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# Space it in the center
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nmos_lower_position = self.nmos.active_offset.scale(0, 1) \
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+ vector(0.5 * self.bitcell.width- 0.5 * self.nmos.active_width, 0)
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self.nmos_lower.place(nmos_lower_position)
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# This aligns it directly above the other tx with gates abutting
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nmos_upper_position = nmos_lower_position \
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+ vector(0, self.nmos.active_height + max(self.active_space, self.poly_space))
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self.nmos_upper.place(nmos_upper_position)
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if OPTS.tech_name == "sky130":
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self.add_implants()
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@ -30,13 +30,15 @@ if not OPTS.check_lvsdrc:
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OPTS.drc_exe = None
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OPTS.lvs_exe = None
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OPTS.pex_exe = None
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if OPTS.tech_name == "sky130":
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OPTS.magic_exe = None
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else:
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debug.info(1, "Finding DRC/LVS/PEX tools.")
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OPTS.drc_exe = get_tool("DRC", ["calibre", "assura", "magic"], drc_name)
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OPTS.lvs_exe = get_tool("LVS", ["calibre", "assura", "netgen"], lvs_name)
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OPTS.pex_exe = get_tool("PEX", ["calibre", "magic"], pex_name)
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if OPTS.tech_name == "sky130":
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OPTS.magic_exe = get_tool("GDS", ["magic"], None)
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OPTS.magic_exe = get_tool("GDS", ["magic"])
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if not OPTS.drc_exe:
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from .none import run_drc, print_drc_stats
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@ -71,7 +73,7 @@ else:
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debug.warning("Did not find a supported PEX tool.")
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if OPTS.tech_name == "sky130":
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if "magic"==OPTS.magic_exe[0]:
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if OPTS.magic_exe and "magic"==OPTS.magic_exe[0]:
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from .magic import filter_gds
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else:
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debug.warning("Did not find Magic.")
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