mirror of https://github.com/VLSIDA/OpenRAM.git
Use pand2 of correct size. Simplify width checking of AND array.
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@ -63,8 +63,9 @@ class write_mask_and_array(design.design):
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def add_modules(self):
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def add_modules(self):
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# Size the AND gate for the number of write drivers it drives, which is equal to the write size.
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# Size the AND gate for the number of write drivers it drives, which is equal to the write size.
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# Assume stage effort of 3 to compute the size
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self.and2 = factory.create(module_type="pand2",
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self.and2 = factory.create(module_type="pand2",
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size=self.write_size)
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size=self.write_size/4.0)
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self.add_mod(self.and2)
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self.add_mod(self.and2)
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@ -92,18 +93,12 @@ class write_mask_and_array(design.design):
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else:
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else:
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self.driver_spacing = self.driver.width
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self.driver_spacing = self.driver.width
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if (self.words_per_row == 1):
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self.wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
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wmask_en_len = (self.write_size * self.driver_spacing)
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debug.check(self.wmask_en_len >= self.and2.width,
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if self.driver_spacing * self.write_size < self.and2.width:
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"Write mask AND is wider than the corresponding write drivers {0} vs {1}.".format(self.and2.width,self.wmask_en_len))
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debug.error("Cannot layout write mask AND array. One pand2 is longer than the corresponding write drivers.")
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else:
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wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
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if wmask_en_len < self.and2.width:
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debug.error("Cannot layout write mask AND array. One pand2 is longer than the corresponding write drivers.")
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self.wmask_en_len = wmask_en_len
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for i in range(self.num_wmasks):
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for i in range(self.num_wmasks):
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base = vector(i * wmask_en_len, 0)
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base = vector(i * self.wmask_en_len, 0)
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self.and2_insts[i].place(base)
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self.and2_insts[i].place(base)
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@ -36,7 +36,6 @@ class pand2(pgate.pgate):
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self.nand = factory.create(module_type="pnand2",height=self.height)
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self.nand = factory.create(module_type="pnand2",height=self.height)
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self.add_mod(self.nand)
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self.add_mod(self.nand)
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# Assume stage effort of 3
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self.inv = factory.create(module_type="pdriver", neg_polarity=True, fanout=3*self.size, height=self.height)
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self.inv = factory.create(module_type="pdriver", neg_polarity=True, fanout=3*self.size, height=self.height)
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self.add_mod(self.inv)
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self.add_mod(self.inv)
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@ -45,7 +45,7 @@ class pdriver(pgate.pgate):
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self.num_stages = len(self.size_list)
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self.num_stages = len(self.size_list)
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else:
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else:
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# Find the optimal number of stages for the given effort
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# Find the optimal number of stages for the given effort
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self.num_stages = max(1,int(round(log(self.fanout)/log(self.stage_effort))))
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self.num_stages = max(1,int(round(self.fanout**(1/self.stage_effort))))
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# Increase the number of stages if we need to fix polarity
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# Increase the number of stages if we need to fix polarity
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if self.neg_polarity and (self.num_stages%2==0):
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if self.neg_polarity and (self.num_stages%2==0):
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