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Enable power routing for failing FreePDK45 tests (VLSIDA/PrivateRAM#97)

This commit is contained in:
Eren Dogan 2023-07-24 19:21:31 -07:00
parent fa74a45d8c
commit 2b15289daf
8 changed files with 0 additions and 24 deletions
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3
compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
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@ -23,9 +23,6 @@ class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test):
openram.init_openram(config_file, is_unit_test=True) openram.init_openram(config_file, is_unit_test=True)
from openram import sram_config from openram import sram_config
if OPTS.tech_name == "freepdk45":
OPTS.route_supplies = False
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0

3
compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py
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@ -23,9 +23,6 @@ class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test):
openram.init_openram(config_file, is_unit_test=True) openram.init_openram(config_file, is_unit_test=True)
from openram import sram_config from openram import sram_config
if OPTS.tech_name == "freepdk45":
OPTS.route_supplies = False
OPTS.num_rw_ports = 0 OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1 OPTS.num_w_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1

3
compiler/tests/20_sram_1bank_2mux_global_test.py
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@ -31,9 +31,6 @@ class sram_1bank_2mux_global_test(openram_test):
num_spare_rows = 0 num_spare_rows = 0
num_spare_cols = 0 num_spare_cols = 0
if OPTS.tech_name == "freepdk45":
OPTS.route_supplies = False
c = sram_config(word_size=8, c = sram_config(word_size=8,
num_words=32, num_words=32,
num_banks=1, num_banks=1,

3
compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py
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@ -30,9 +30,6 @@ class sram_1bank_2mux_wmask_spare_cols_test(openram_test):
num_spare_rows = 0 num_spare_rows = 0
num_spare_cols = 0 num_spare_cols = 0
if OPTS.tech_name == "freepdk45":
OPTS.route_supplies = False
c = sram_config(word_size=8, c = sram_config(word_size=8,
write_size=4, write_size=4,
num_words=64, num_words=64,

3
compiler/tests/20_sram_1bank_2mux_wmask_test.py
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@ -30,9 +30,6 @@ class sram_1bank_2mux_wmask_test(openram_test):
num_spare_rows = 0 num_spare_rows = 0
num_spare_cols = 0 num_spare_cols = 0
if OPTS.tech_name == "freepdk45":
OPTS.route_supplies = False
c = sram_config(word_size=8, c = sram_config(word_size=8,
write_size=4, write_size=4,
num_words=64, num_words=64,

3
compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py
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@ -23,9 +23,6 @@ class sram_1bank_4mux_1rw_1r_test(openram_test):
openram.init_openram(config_file, is_unit_test=True) openram.init_openram(config_file, is_unit_test=True)
from openram import sram_config from openram import sram_config
if OPTS.tech_name == "freepdk45":
OPTS.route_supplies = False
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0

3
compiler/tests/20_sram_1bank_4mux_test.py
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@ -30,9 +30,6 @@ class sram_1bank_4mux_test(openram_test):
num_spare_rows = 0 num_spare_rows = 0
num_spare_cols = 0 num_spare_cols = 0
if OPTS.tech_name == "freepdk45":
OPTS.route_supplies = False
c = sram_config(word_size=4, c = sram_config(word_size=4,
num_words=64, num_words=64,
num_banks=1, num_banks=1,

3
compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
View File

@ -23,9 +23,6 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
openram.init_openram(config_file, is_unit_test=True) openram.init_openram(config_file, is_unit_test=True)
from openram import sram_config from openram import sram_config
if OPTS.tech_name == "freepdk45":
OPTS.route_supplies = False
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0