mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 20:00:14 +02:00
Refactor dynamic cell name to utilize base class
This commit is contained in:
@@ -9,7 +9,7 @@
|
||||
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os,re
|
||||
import sys, os,re
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
import debug
|
||||
|
||||
Reference in New Issue
Block a user