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Merged with dev, addressed conflict in port data

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Hunter Nichols
2021-06-21 17:23:32 -07:00
parent 8ee6d3be6c 3502bec231
commit 294ccf602e
23 changed files with 307 additions and 139 deletions
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compiler/modules/port_data.py
+7 -12
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@@ -21,24 +21,19 @@ class port_data(design.design):
Port 0 always has the RBL on the left while port 1 is on the right.
"""
def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="", rows=None, cols=None, dimension_override=False):
sram_config.set_local_config(self)
if dimension_override:
self.num_rows = rows
self.num_cols = cols
self.word_size = sram_config.word_size
def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="",):
sram_config.set_local_config(self)
self.port = port
if self.write_size is not None:
self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
else:
self.num_wmasks = 0
if num_spare_cols:
self.num_spare_cols = num_spare_cols
elif self.num_spare_cols is None:
if num_spare_cols is not None:
self.num_spare_cols = num_spare_cols + self.num_spare_cols
if self.num_spare_cols is None:
self.num_spare_cols = 0
if not bit_offsets:
bitcell = factory.create(module_type=OPTS.bitcell)
if(cell_properties.use_strap == True and OPTS.num_ports == 1):
@@ -869,4 +864,4 @@ class port_data(design.design):
Clear mux exclusions to allow different bit tests.
"""
if self.column_mux_array:
self.column_mux_array.init_graph_params()
self.column_mux_array.init_graph_params()