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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-30 01:48:33 +02:00
Precharge updates.
Enable different layers for bitlines. Jog bitlines to fit precharge transistors for close proximity bitlines. PEP8 cleanup.
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@@ -12,6 +12,7 @@ from vector import vector
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from sram_factory import factory
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from globals import OPTS
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class precharge_array(design.design):
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"""
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Dynamically generated precharge array of all bitlines. Cols is number
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@@ -68,11 +69,8 @@ class precharge_array(design.design):
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size=self.size,
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bitcell_bl=self.bitcell_bl,
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bitcell_br=self.bitcell_br)
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self.add_mod(self.pc_cell)
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def add_layout_pins(self):
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self.add_layout_pin(text="en_bar",
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@@ -86,20 +84,9 @@ class precharge_array(design.design):
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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bl_pin = inst.get_pin("bl")
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self.add_layout_pin(text="bl_{0}".format(i),
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layer="m2",
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offset=bl_pin.ll(),
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width=drc("minwidth_m2"),
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height=bl_pin.height())
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br_pin = inst.get_pin("br")
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self.add_layout_pin(text="br_{0}".format(i),
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layer="m2",
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offset=br_pin.ll(),
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width=drc("minwidth_m2"),
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height=bl_pin.height())
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self.copy_layout_pin(inst, "bl", "bl_{0}".format(i))
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self.copy_layout_pin(inst, "br", "br_{0}".format(i))
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def create_insts(self):
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"""Creates a precharge array by horizontally tiling the precharge cell"""
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self.local_insts = []
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@@ -112,7 +99,6 @@ class precharge_array(design.design):
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self.local_insts.append(inst)
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self.connect_inst(["bl_{0}".format(i), "br_{0}".format(i), "en_bar", "vdd"])
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def place_insts(self):
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""" Places precharge array by horizontally tiling the precharge cell"""
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from tech import cell_properties
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@@ -130,8 +116,11 @@ class precharge_array(design.design):
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xoffset = xoffset + self.pc_cell.width
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def get_en_cin(self):
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"""Get the relative capacitance of all the clk connections in the precharge array"""
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#Assume single port
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"""
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Get the relative capacitance of all the clk connections
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in the precharge array
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"""
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# Assume single port
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precharge_en_cin = self.pc_cell.get_en_cin()
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return precharge_en_cin*self.columns
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return precharge_en_cin * self.columns
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