mirror of https://github.com/VLSIDA/OpenRAM.git
Add missing via in dff array
This commit is contained in:
parent
76bc4e1fc2
commit
280582d4d6
|
|
@ -119,12 +119,12 @@ class dff_array(design.design):
|
||||||
# Add connections every 4 cells
|
# Add connections every 4 cells
|
||||||
for col in range(0, self.columns, 4):
|
for col in range(0, self.columns, 4):
|
||||||
vdd_pin=self.dff_insts[0, col].get_pin("vdd")
|
vdd_pin=self.dff_insts[0, col].get_pin("vdd")
|
||||||
self.add_power_pin("vdd", vdd_pin.lc())
|
self.add_power_pin("vdd", vdd_pin.lc(), start_layer=vdd_pin.layer)
|
||||||
|
|
||||||
# Add connections every 4 cells
|
# Add connections every 4 cells
|
||||||
for col in range(0, self.columns, 4):
|
for col in range(0, self.columns, 4):
|
||||||
gnd_pin=self.dff_insts[0, col].get_pin("gnd")
|
gnd_pin=self.dff_insts[0, col].get_pin("gnd")
|
||||||
self.add_power_pin("gnd", gnd_pin.rc())
|
self.add_power_pin("gnd", gnd_pin.rc(), start_layer=vdd_pin.layer)
|
||||||
|
|
||||||
def add_layout_pins(self):
|
def add_layout_pins(self):
|
||||||
for row in range(self.rows):
|
for row in range(self.rows):
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue