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Rewrite blockage routines in router. Clean up GdsMill code.

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Matt Guthaus
2018-08-29 15:34:45 -07:00
parent 04b7c419f1
commit 27bb1d2ee7
14 changed files with 256 additions and 176 deletions
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compiler/tests/19_single_bank_test.py
+1 -1
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@@ -20,7 +20,7 @@ class single_bank_test(openram_test):
debug.info(1, "No column mux")
a = bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="bank1_single")
self.local_check(a)
debug.info(1, "Two way column mux")
a = bank(word_size=4, num_words=32, words_per_row=2, num_banks=1, name="bank2_single")
self.local_check(a)
compiler/tests/20_sram_1bank_test.py
+9 -9
View File
@@ -21,17 +21,17 @@ class sram_1bank_test(openram_test):
a = sram(word_size=4, num_words=16, num_banks=1, name="sram1")
self.local_check(a, final_verification=True)
debug.info(1, "Single bank two way column mux with control logic")
a = sram(word_size=4, num_words=32, num_banks=1, name="sram2")
self.local_check(a, final_verification=True)
# debug.info(1, "Single bank two way column mux with control logic")
# a = sram(word_size=4, num_words=32, num_banks=1, name="sram2")
# self.local_check(a, final_verification=True)
debug.info(1, "Single bank, four way column mux with control logic")
a = sram(word_size=4, num_words=64, num_banks=1, name="sram3")
self.local_check(a, final_verification=True)
# debug.info(1, "Single bank, four way column mux with control logic")
# a = sram(word_size=4, num_words=64, num_banks=1, name="sram3")
# self.local_check(a, final_verification=True)
debug.info(1, "Single bank, eight way column mux with control logic")
a = sram(word_size=2, num_words=128, num_banks=1, name="sram4")
self.local_check(a, final_verification=True)
# debug.info(1, "Single bank, eight way column mux with control logic")
# a = sram(word_size=2, num_words=128, num_banks=1, name="sram4")
# self.local_check(a, final_verification=True)
globals.end_openram()