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Rewrite blockage routines in router. Clean up GdsMill code.

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This commit is contained in:
Matt Guthaus
2018-08-29 15:34:45 -07:00
parent 04b7c419f1
commit 27bb1d2ee7
14 changed files with 256 additions and 176 deletions
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compiler/modules/delay_chain.py
+2 -2
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@@ -186,7 +186,7 @@ class delay_chain(design.design):
continue
for pin_name in ["vdd", "gnd"]:
pin = load.get_pin(pin_name)
self.add_power_pin(pin_name, pin.rc())
self.add_power_pin(pin_name, pin.rc(),rotate=0)
else:
# We have an even number of rows, so need to get the last gnd rail
inv = self.driver_inst_list[-1]
@@ -195,7 +195,7 @@ class delay_chain(design.design):
continue
pin_name = "gnd"
pin = load.get_pin(pin_name)
self.add_power_pin(pin_name, pin.rc())
self.add_power_pin(pin_name, pin.rc(),rotate=0)
# input is A pin of first inverter
compiler/modules/replica_bitline.py
+1 -1
View File
@@ -192,7 +192,7 @@ class replica_bitline(design.design):
# Replica bitcell needs to be routed up to M3
pin=self.rbc_inst.get_pin("vdd")
# Don't rotate this via to vit in FreePDK45
self.add_power_pin("vdd", pin.center(), False)
self.add_power_pin("vdd", pin.center(), rotate=0)
for pin in self.rbc_inst.get_pins("gnd"):
self.add_power_pin("gnd", pin.center())