Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.

compiler/modules/bank.py

@@ -243,9 +243,13 @@ class bank(design.design):
             self.add_mod(self.precharge_array[port])
 
         if self.col_addr_size > 0:
-            self.column_mux_array = self.mod_column_mux_array(columns=self.num_cols, 
+            self.column_mux_array = []
-                                                              word_size=self.word_size)
+            for port in range(self.total_ports):
-            self.add_mod(self.column_mux_array)
+                self.column_mux_array.append(self.mod_column_mux_array(columns=self.num_cols, 
+                                                                       word_size=self.word_size,
+                                                                       bitcell_bl=self.read_bl_list[port],
+                                                                       bitcell_br=self.read_br_list[port]))
+                self.add_mod(self.column_mux_array[port])
 
 
         self.sense_amp_array = self.mod_sense_amp_array(word_size=self.word_size, 
@@ -325,7 +329,7 @@ class bank(design.design):
         self.col_mux_array_inst = []
         for port in range(self.total_ports):
             self.col_mux_array_inst.append(self.add_inst(name="column_mux_array{}".format(port),
-                                                         mod=self.column_mux_array))
+                                                         mod=self.column_mux_array[port]))
 
             temp = []
             for col in range(self.num_cols):
@@ -342,7 +346,7 @@ class bank(design.design):
     def place_column_mux_array(self):
         """ Placing Column Mux when words_per_row > 1 . """
         if self.col_addr_size > 0:
-            self.column_mux_height = self.column_mux_array.height + self.m2_gap
+            self.column_mux_height = self.column_mux_array[0].height + self.m2_gap
         else:
             self.column_mux_height = 0
             return

compiler/modules/single_level_column_mux_array.py

@@ -14,12 +14,18 @@ class single_level_column_mux_array(design.design):
     Array of column mux to read the bitlines through the 6T.
     """
 
-    def __init__(self, columns, word_size):
+    unique_id = 1
-        design.design.__init__(self, "columnmux_array")
+    
+    def __init__(self, columns, word_size, bitcell_bl="bl", bitcell_br="br"):
+        name="single_level_column_mux_array_{}".format(single_level_column_mux_array.unique_id)
+        single_level_column_mux_array.unique_id += 1
+        design.design.__init__(self, name)
         debug.info(1, "Creating {0}".format(self.name))
         self.columns = columns
         self.word_size = word_size
         self.words_per_row = int(self.columns / self.word_size)
+        self.bitcell_bl = bitcell_bl
+        self.bitcell_br = bitcell_br
         
         self.create_netlist()
         if not OPTS.netlist_only:
@@ -56,7 +62,7 @@ class single_level_column_mux_array(design.design):
 
     def add_modules(self):
         # FIXME: Why is this 8x?
-        self.mux = single_level_column_mux(tx_size=8)
+        self.mux = single_level_column_mux(tx_size=8, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br)
         self.add_mod(self.mux)
 
 

compiler/modules/wordline_driver.py

@@ -52,10 +52,6 @@ class wordline_driver(design.design):
     def add_modules(self):
         # This is just used for measurements,
         # so don't add the module
-        from importlib import reload
-        c = reload(__import__(OPTS.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.bitcell)
-        self.bitcell = self.mod_bitcell()
 
         self.inv = pinv()
         self.add_mod(self.inv)
@@ -134,12 +130,8 @@ class wordline_driver(design.design):
         inv2_xoffset = nand2_xoffset + self.nand2.width
         
         self.width = inv2_xoffset + self.inv.height
-        if self.bitcell.height > self.inv.height:
+        driver_height = self.inv.height
-            self.height = self.bitcell.height * self.rows
+        self.height = self.inv.height * self.rows
-            driver_height = self.bitcell.height
-        else:
-            self.height = self.inv.height * self.rows
-            driver_height = self.inv.height
         
         for row in range(self.rows):
             if (row % 2):

compiler/pgates/single_level_column_mux.py

@@ -12,12 +12,17 @@ class single_level_column_mux(design.design):
     Creates a single columnmux cell.
     """
 
-    def __init__(self, tx_size):
+    unique_id = 1
-        name="single_level_column_mux_{}".format(tx_size)
+    
+    def __init__(self, tx_size, bitcell_bl="bl", bitcell_br="br"):
+        name="single_level_column_mux_{}_no{}".format(tx_size,single_level_column_mux.unique_id)
+        single_level_column_mux.unique_id += 1
         design.design.__init__(self, name)
         debug.info(2, "create single column mux cell: {0}".format(name))
 
         self.tx_size = tx_size
+        self.bitcell_bl = bitcell_bl
+        self.bitcell_br = bitcell_br
         
         self.create_netlist()
         if not OPTS.netlist_only:
@@ -59,8 +64,8 @@ class single_level_column_mux(design.design):
     def add_bitline_pins(self):
         """ Add the top and bottom pins to this cell """
 
-        bl_pos = vector(self.bitcell.get_pin("bl").lx(), 0)
+        bl_pos = vector(self.bitcell.get_pin(self.bitcell_bl).lx(), 0)
-        br_pos = vector(self.bitcell.get_pin("br").lx(), 0)
+        br_pos = vector(self.bitcell.get_pin(self.bitcell_br).lx(), 0)
 
         # bl and br
         self.add_layout_pin(text="bl",