luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

extend input rail

This commit is contained in:
Jesse Cirimelli-Low 2021-06-14 15:13:17 -07:00
parent 73cc6b3891
commit 25bc178132
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
compiler/modules/hierarchical_predecode.py
View File

@ -122,7 +122,7 @@ class hierarchical_predecode(design.design):
self.input_rails = self.create_vertical_bus(layer=self.bus_layer, self.input_rails = self.create_vertical_bus(layer=self.bus_layer,
offset=offset, offset=offset,
names=input_names, names=input_names,
length=self.height - 2 * self.bus_pitch, length=self.height - self.bus_pitch,
pitch=self.bus_pitch) pitch=self.bus_pitch)
invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)] invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)]
@ -132,7 +132,7 @@ class hierarchical_predecode(design.design):
self.decode_rails = self.create_vertical_bus(layer=self.bus_layer, self.decode_rails = self.create_vertical_bus(layer=self.bus_layer,
offset=offset, offset=offset,
names=decode_names, names=decode_names,
length=self.height - 2 * self.bus_pitch, length=self.height - self.bus_pitch,
pitch=self.bus_pitch) pitch=self.bus_pitch)
def create_input_inverters(self): def create_input_inverters(self):