Merge branch 'dev' into bisr

compiler/tests/02_library_lvs_test.py

@@ -45,7 +45,9 @@ class library_lvs_test(openram_test):
 
 def setup_files():
     gds_dir = OPTS.openram_tech + "/gds_lib"
-    sp_dir = OPTS.openram_tech + "/sp_lib"
+    sp_dir = OPTS.openram_tech + "/lvs_lib"
+    if not os.path.exists(sp_dir):
+        sp_dir = OPTS.openram_tech + "/sp_lib"
     files = os.listdir(gds_dir)
     nametest = re.compile("\.gds$", re.IGNORECASE)
     gds_files = list(filter(nametest.search, files))

compiler/tests/03_ptx_1finger_nmos_test.py

@@ -15,6 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class ptx_1finger_nmos_test(openram_test):
 
     def runTest(self):

compiler/tests/04_precharge_pbitcell_test.py

@@ -0,0 +1,52 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class precharge_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check precharge in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        factory.reset()
+        debug.info(2, "Checking precharge for pbitcell (innermost connections)")
+        tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(tx)
+
+        factory.reset()
+        debug.info(2, "Checking precharge for pbitcell (innermost connections)")
+        tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
+        self.local_check(tx)
+
+        factory.reset()
+        debug.info(2, "Checking precharge for pbitcell (outermost connections)")
+        tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2")
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_precharge_test.py

@@ -15,6 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class precharge_test(openram_test):
 
     def runTest(self):
@@ -26,27 +27,6 @@ class precharge_test(openram_test):
         tx = factory.create(module_type="precharge", size=1)
         self.local_check(tx)
         
-        # check precharge in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-
-        factory.reset()
-        debug.info(2, "Checking precharge for pbitcell (innermost connections)")
-        tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(tx)
-
-        factory.reset()
-        debug.info(2, "Checking precharge for pbitcell (innermost connections)")
-        tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
-        self.local_check(tx)
-        
-        factory.reset()
-        debug.info(2, "Checking precharge for pbitcell (outermost connections)")
-        tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2")
-        self.local_check(tx)
-
         globals.end_openram()
         
 # run the test from the command line

compiler/tests/04_single_level_column_mux_pbitcell_test.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+#@unittest.skip("SKIPPING 04_driver_test")
+
+class single_level_column_mux_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check single level column mux in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        factory.reset()
+        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
+        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(tx)
+
+        factory.reset()
+        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
+        tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_single_level_column_mux_test.py

@@ -22,30 +22,14 @@ class single_level_column_mux_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
-        
+
         # check single level column mux in single port
         debug.info(2, "Checking column mux")
         tx = factory.create(module_type="single_level_column_mux", tx_size=8)
         self.local_check(tx)
-        
-        # check single level column mux in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-
-        factory.reset()
-        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
-        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(tx)
-        
-        factory.reset()
-        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
-        tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
-        self.local_check(tx)
 
         globals.end_openram()
-        
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()

compiler/tests/05_replica_pbitcell_array_test.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California 
+# Copyright (c) 2016-2019 Regents of the University of California
 # All rights reserved.
 #
 import unittest
@@ -13,7 +13,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class replica_bitcell_array_test(openram_test):
+class replica_pbitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -41,7 +41,7 @@ class replica_bitcell_array_test(openram_test):
         debug.info(2, "Testing 4x4 array for pbitcell")
         a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0])
         self.local_check(a)
-        
+
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/06_hierarchical_decoder_pbitcell_test.py

@@ -0,0 +1,73 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class hierarchical_decoder_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        # check hierarchical decoder for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
+        self.local_check(a)
+
+        factory.reset()
+        debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
+        self.local_check(a)
+
+        factory.reset()
+        debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=23)
+        self.local_check(a)
+
+        debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
+        self.local_check(a)
+
+        factory.reset()
+        debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=65)
+        self.local_check(a)
+
+        debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=128)
+        self.local_check(a)
+
+        factory.reset()
+        debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=341)
+        self.local_check(a)
+
+        debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/06_hierarchical_decoder_test.py

@@ -20,92 +20,40 @@ class hierarchical_decoder_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
-        # Doesn't require hierarchical decoder
-        # debug.info(1, "Testing 4 row sample for hierarchical_decoder")
-        # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4)
-        # self.local_check(a)
-
-        # Doesn't require hierarchical decoder
-        # debug.info(1, "Testing 8 row sample for hierarchical_decoder")
-        # a = hierarchical_decoder.hierarchical_decoder(name="hd2", rows=8)
-        # self.local_check(a)
 
         # check hierarchical decoder for single port
         debug.info(1, "Testing 16 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=16)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
         self.local_check(a)
 
         debug.info(1, "Testing 17 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=17)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
         self.local_check(a)
 
         debug.info(1, "Testing 23 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=23)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=23)
         self.local_check(a)
 
         debug.info(1, "Testing 32 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=32)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
         self.local_check(a)
 
         debug.info(1, "Testing 65 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=65)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=65)
         self.local_check(a)
 
         debug.info(1, "Testing 128 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=128)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=128)
         self.local_check(a)
 
         debug.info(1, "Testing 341 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=341)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=341)
         self.local_check(a)
 
         debug.info(1, "Testing 512 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=512)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
         self.local_check(a)
         
-        # check hierarchical decoder for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=16)
-        self.local_check(a)
-
-        factory.reset()
-        debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=17)
-        self.local_check(a)
-
-        factory.reset()
-        debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=23)
-        self.local_check(a)
-
-        debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=32)
-        self.local_check(a)
-
-        factory.reset()
-        debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=65)
-        self.local_check(a)
-
-        debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=128)
-        self.local_check(a)
-
-        factory.reset()
-        debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=341)
-        self.local_check(a)
-
-        debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=512)
-        self.local_check(a)
-
         globals.end_openram()
         
 # run the test from the command line

compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py

@@ -0,0 +1,41 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class hierarchical_predecode2x4_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # checking hierarchical precode 2x4 for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
+        a = factory.create(module_type="hierarchical_predecode2x4")
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/06_hierarchical_predecode2x4_test.py

@@ -26,18 +26,8 @@ class hierarchical_predecode2x4_test(openram_test):
         a = factory.create(module_type="hierarchical_predecode2x4")
         self.local_check(a)
 
-        # checking hierarchical precode 2x4 for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-        
-        debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
-        a = factory.create(module_type="hierarchical_predecode2x4")
-        self.local_check(a)
-        
         globals.end_openram()
-        
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()

compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py

@@ -0,0 +1,41 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class hierarchical_predecode3x8_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # checking hierarchical precode 3x8 for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
+        a = factory.create(module_type="hierarchical_predecode3x8")
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/06_hierarchical_predecode3x8_test.py

@@ -25,16 +25,6 @@ class hierarchical_predecode3x8_test(openram_test):
         debug.info(1, "Testing sample for hierarchy_predecode3x8")
         a = factory.create(module_type="hierarchical_predecode3x8")
         self.local_check(a)
-        
-        # checking hierarchical precode 3x8 for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-        
-        debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
-        a = factory.create(module_type="hierarchical_predecode3x8")
-        self.local_check(a)
 
         globals.end_openram()
 

compiler/tests/07_single_level_column_mux_array_pbitcell_test.py

@@ -0,0 +1,55 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class single_level_column_mux_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        import single_level_column_mux_array
+
+        # check single level column mux array in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        factory.reset()
+        debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
+        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(a)
+
+        debug.info(1, "Testing sample for 4-way column_mux_array  in multi-port")
+        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(a)
+
+        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (innermost connections)")
+        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(a)
+
+        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (outermost connections)")
+        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/07_single_level_column_mux_array_test.py

@@ -20,7 +20,7 @@ class single_level_column_mux_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         import single_level_column_mux_array
-        
+
         # check single level column mux array in single port
         debug.info(1, "Testing sample for 2-way column_mux_array")
         a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8)
@@ -33,32 +33,9 @@ class single_level_column_mux_test(openram_test):
         debug.info(1, "Testing sample for 8-way column_mux_array")
         a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4)
         self.local_check(a)
-        
-        # check single level column mux array in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-
-        factory.reset()
-        debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
-        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 4-way column_mux_array  in multi-port")
-        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (innermost connections)")
-        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-        
-        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (outermost connections)")
-        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
-        self.local_check(a)
 
         globals.end_openram()
-        
+
 
 # run the test from the command line
 if __name__ == "__main__":

compiler/tests/08_precharge_array_1rw1r_test.py

@@ -0,0 +1,50 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class precharge_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        
+        # check precharge array in multi-port
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+
+        factory.reset()
+        debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
+        pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(pc)
+        
+        # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")
+        # pc = precharge_array.precharge_array(name="pre3", columns=3, bitcell_bl="bl0", bitcell_br="br0")
+        # self.local_check(pc)
+        
+        # debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)")
+        # pc = precharge_array.precharge_array(name="pre4", columns=3, bitcell_bl="bl2", bitcell_br="br2")
+        # self.local_check(pc)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/08_precharge_array_test.py

@@ -25,25 +25,6 @@ class precharge_test(openram_test):
         debug.info(2, "Checking 3 column precharge")
         pc = factory.create(module_type="precharge_array", columns=3)
         self.local_check(pc)
-        
-        # check precharge array in multi-port
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 0
-
-        factory.reset()
-        debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
-        pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(pc)
-        
-        # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")
-        # pc = precharge_array.precharge_array(name="pre3", columns=3, bitcell_bl="bl0", bitcell_br="br0")
-        # self.local_check(pc)
-        
-        # debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)")
-        # pc = precharge_array.precharge_array(name="pre4", columns=3, bitcell_bl="bl2", bitcell_br="br2")
-        # self.local_check(pc)
 
         globals.end_openram()
 

compiler/tests/08_wordline_driver_pbitcell_test.py

@@ -0,0 +1,44 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+#@unittest.skip("SKIPPING 04_driver_test")
+
+class wordline_driver_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check wordline driver for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Checking driver (multi-port case)")
+        tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/08_wordline_driver_test.py

@@ -28,19 +28,8 @@ class wordline_driver_test(openram_test):
         tx = factory.create(module_type="wordline_driver", rows=8, cols=32)
         self.local_check(tx)
 
-        # check wordline driver for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Checking driver (multi-port case)")
-        tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
-        self.local_check(tx)
-
         globals.end_openram()
-        
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()

compiler/tests/09_sense_amp_array_test.py

@@ -22,6 +22,10 @@ class sense_amp_test(openram_test):
         globals.init_openram(config_file)
 
         # check sense amp array for single port
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
+        self.local_check(a)
+
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
         self.local_check(a)
@@ -29,24 +33,9 @@ class sense_amp_test(openram_test):
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
         self.local_check(a)
-        
-        # check sense amp array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
 
-        factory.reset()
-        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
-        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
-        self.local_check(a)
-
-        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
-        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
-        self.local_check(a)
-        
         globals.end_openram()
-        
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()

compiler/tests/09_sense_amp_array_test_pbitcell.py

@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class sense_amp_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        #check sense amp array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
+        self.local_check(a)
+
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_driver_array_pbitcell_test.py

@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class write_driver_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check write driver array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_driver_array_test.py

@@ -29,22 +29,7 @@ class write_driver_test(openram_test):
         debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
         self.local_check(a)
-        
-        # check write driver array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
 
-        factory.reset()
-        debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
-        self.local_check(a)
-
-        debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
-        self.local_check(a)
-        
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/10_write_driver_array_wmask_pbitcell_test.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class write_driver_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check write driver array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_driver_array_wmask_test.py

@@ -36,21 +36,6 @@ class write_driver_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
         self.local_check(a)
 
-        # check write driver array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4)
-        self.local_check(a)
-
-        debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
-        self.local_check(a)
-
         globals.end_openram()
 
 

compiler/tests/10_write_mask_and_array_pbitcell_test.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class write_mask_and_array_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check write driver array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)")
+        a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2 (multi-port case)")
+        a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_mask_and_array_test.py

@@ -36,21 +36,6 @@ class write_mask_and_array_test(openram_test):
         a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
         self.local_check(a)
 
-        # check write driver array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)")
-        a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
-        self.local_check(a)
-
-        debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2 (multi-port case)")
-        a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
-        self.local_check(a)
-
         globals.end_openram()
 
 

compiler/tests/18_port_data_1rw_1r_test.py

@@ -0,0 +1,78 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class port_data_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        from sram_config import sram_config
+
+        OPTS.bitcell = "bitcell_1w_1r"
+        OPTS.num_rw_ports = 0
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        c = sram_config(word_size=4,
+                        num_words=16)
+
+        c.words_per_row=1
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "No column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+        
+        c.num_words=32
+        c.words_per_row=2
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Two way column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+
+        c.num_words=64
+        c.words_per_row=4
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Four way column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+
+        c.word_size=2
+        c.num_words=128
+        c.words_per_row=8
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Eight way column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+        
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/18_port_data_test.py

@@ -55,52 +55,6 @@ class port_data_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=0)
         self.local_check(a)
         
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.num_rw_ports = 0
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-        
-        c.num_words=16
-        c.words_per_row=1
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "No column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-        
-        c.num_words=32
-        c.words_per_row=2
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Two way column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-
-        c.num_words=64
-        c.words_per_row=4
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Four way column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-
-        c.word_size=2
-        c.num_words=128
-        c.words_per_row=8
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Eight way column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-        
         globals.end_openram()
         
 # run the test from the command line

compiler/tests/19_bank_select_pbitcell_test.py

@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class bank_select_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.bitcell = "pbitcell"
+        debug.info(1, "No column mux, rw control logic")
+        a = factory.create(module_type="bank_select", port="rw")
+        self.local_check(a)
+
+        OPTS.num_rw_ports = 0
+        OPTS.num_w_ports = 1
+        OPTS.num_r_ports = 1
+
+        debug.info(1, "No column mux, w control logic")
+        a = factory.create(module_type="bank_select", port="w")
+        self.local_check(a)
+
+        debug.info(1, "No column mux, r control logic")
+        a = factory.create(module_type="bank_select", port="r")
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/19_bank_select_test.py

@@ -24,26 +24,9 @@ class bank_select_test(openram_test):
         debug.info(1, "No column mux, rw control logic")
         a = factory.create(module_type="bank_select", port="rw")
         self.local_check(a)
-        
-        OPTS.bitcell = "pbitcell"
-        debug.info(1, "No column mux, rw control logic")
-        a = factory.create(module_type="bank_select", port="rw")
-        self.local_check(a)
-        
-        OPTS.num_rw_ports = 0
-        OPTS.num_w_ports = 1
-        OPTS.num_r_ports = 1
 
-        debug.info(1, "No column mux, w control logic")
-        a = factory.create(module_type="bank_select", port="w")
-        self.local_check(a)
-        
-        debug.info(1, "No column mux, r control logic")
-        a = factory.create(module_type="bank_select", port="r")
-        self.local_check(a)
-        
         globals.end_openram()
-        
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()

compiler/tests/21_hspice_delay_test.py

@@ -60,29 +60,36 @@ class timing_sram_test(openram_test):
         data, port_data = d.analyze(probe_address, probe_data, slews, loads)
         #Combine info about port into all data
         data.update(port_data[0])
-     
+
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'delay_hl': [0.2383338],
-                           'delay_lh': [0.2383338],
-                           'leakage_power': 0.0014532999999999998,
-                           'min_period': 0.898,
-                           'read0_power': [0.30059800000000003],
-                           'read1_power': [0.30061810000000005],
-                           'slew_hl': [0.25358420000000004],
-                           'slew_lh': [0.25358420000000004],
-                           'write0_power': [0.34616749999999996],
-                           'write1_power': [0.2792924]}
+            golden_data = {'min_period': 0.898,
+                           'write1_power': [0.2659137999999999],
+                           'disabled_write0_power': [0.1782495],
+                           'disabled_read0_power': [0.14490679999999997],
+                           'write0_power': [0.3330119],
+                           'disabled_write1_power': [0.1865223],
+                           'leakage_power': 0.0014532,
+                           'disabled_read1_power': [0.1627516],
+                           'slew_lh': [0.25367799999999996],
+                           'slew_hl': [0.25367799999999996],
+                           'delay_lh': [0.23820930000000004],
+                           'delay_hl': [0.23820930000000004],
+                           'read1_power': [0.3005756],
+                           'read0_power': [0.3005888]}
         elif OPTS.tech_name == "scn4m_subm":
-            golden_data = {'delay_hl': [1.7448],
-                           'delay_lh': [1.7448],
-                           'leakage_power': 0.0006356744000000001,
+            golden_data = {'leakage_power': 0.0006356576000000001,
+                           'write1_power': [11.292700000000002],
+                           'read0_power': [12.98],
+                           'disabled_write1_power': [8.3707],
+                           'write0_power': [14.4447], 'delay_hl': [1.7445000000000002],
+                           'disabled_read0_power': [6.4325],
+                           'slew_hl': [1.7437],
+                           'disabled_write0_power': [8.1307],
+                           'slew_lh': [1.7437],
+                           'read1_power': [12.9869],
+                           'disabled_read1_power': [7.706],
                            'min_period': 6.25,
-                           'read0_power': [12.9846],
-                           'read1_power': [12.9722],
-                           'slew_hl': [1.7433],
-                           'slew_lh': [1.7433],
-                           'write0_power': [14.8772],
-                           'write1_power': [11.7217]}
+                           'delay_lh': [1.7445000000000002]}
         else:
             self.assertTrue(False) # other techs fail
         # Check if no too many or too few results

compiler/tests/21_ngspice_delay_test.py

@@ -55,27 +55,35 @@ class timing_sram_test(openram_test):
         data.update(port_data[0])
 
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'delay_hl': [0.2264205],
-                           'delay_lh': [0.2264205],
-                           'leakage_power': 0.0021017429999999997,
-                           'min_period': 0.859,
-                           'read0_power': [0.3339161],
-                           'read1_power': [0.31329440000000003],
-                           'slew_hl': [0.2590786],
-                           'slew_lh': [0.2590786],
-                           'write0_power': [0.36360849999999995],
-                           'write1_power': [0.3486931]}
+            golden_data = {'slew_lh': [0.2592187],
+                           'slew_hl': [0.2592187],
+                           'delay_lh': [0.2465583],
+                           'disabled_write0_power': [0.1924678],
+                           'disabled_read0_power': [0.152483],
+                           'write0_power': [0.3409064],
+                           'disabled_read1_power': [0.1737818],
+                           'read0_power': [0.3096708],
+                           'read1_power': [0.3107916],
+                           'delay_hl': [0.2465583],
+                           'write1_power': [0.26915849999999997],
+                           'leakage_power': 0.002044307,
+                           'min_period': 0.898,
+                           'disabled_write1_power': [0.201411]}
         elif OPTS.tech_name == "scn4m_subm":
-            golden_data = {'delay_hl': [1.85985],
-                           'delay_lh': [1.85985],
+            golden_data = {'read1_power': [12.11658],
+                           'write1_power': [10.52653],
+                           'read0_power': [11.956710000000001],
+                           'disabled_write0_power': [7.673665],
+                           'disabled_write1_power': [7.981922000000001],
+                           'slew_lh': [1.868836],
+                           'slew_hl': [1.868836],
+                           'delay_hl': [1.8598510000000001],
+                           'delay_lh': [1.8598510000000001],
                            'leakage_power': 0.008613619,
+                           'disabled_read0_power': [5.904712],
                            'min_period': 6.875,
-                           'read0_power': [12.656310000000001],
-                           'read1_power': [12.11682],
-                           'slew_hl': [1.868942],
-                           'slew_lh': [1.868942],
-                           'write0_power': [13.978110000000001],
-                           'write1_power': [11.437930000000001]}
+                           'disabled_read1_power': [7.132159],
+                           'write0_power': [13.406400000000001]}
         else:
             self.assertTrue(False) # other techs fail
 

compiler/tests/25_verilog_sram_test.py

@@ -19,7 +19,9 @@ class verilog_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
-
+        OPTS.route_supplies=False
+        OPTS.check_lvsdrc=False
+        OPTS.netlist_only=True
         from sram import sram
         from sram_config import sram_config
         c = sram_config(word_size=2,

compiler/tests/30_openram_back_end_test.py

@@ -51,7 +51,7 @@ class openram_back_end_test(openram_test):
             debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage")
             exe_name = "{0}/openram.py ".format(OPENRAM_HOME)
         else:
-            exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) 
+            exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME)
         config_name = "{0}/tests/configs/config_back_end.py".format(OPENRAM_HOME)
         cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name,
                                                                           out_file,
@@ -64,33 +64,32 @@ class openram_back_end_test(openram_test):
         
         # assert an error until we actually check a resul
         for extension in ["gds", "v", "lef", "sp"]:
-            filename = "{0}/{1}.{2}".format(out_path,out_file,extension)
-            debug.info(1,"Checking for file: " + filename)
-            self.assertEqual(os.path.exists(filename),True)
+            filename = "{0}/{1}.{2}".format(out_path, out_file, extension)
+            debug.info(1, "Checking for file: " + filename)
+            self.assertEqual(os.path.exists(filename), True)
 
         # Make sure there is any .lib file
         import glob
         files = glob.glob('{0}/*.lib'.format(out_path))
         self.assertTrue(len(files)>0)
         
-        # Make sure there is any .html file 
+        # Make sure there is any .html file
         if os.path.exists(out_path):
             datasheets = glob.glob('{0}/*html'.format(out_path))
             self.assertTrue(len(datasheets)>0)
         
         # grep any errors from the output
-        output_log = open("{0}/output.log".format(out_path),"r")
+        output_log = open("{0}/output.log".format(out_path), "r")
         output = output_log.read()
         output_log.close()
-        self.assertEqual(len(re.findall('ERROR',output)),0)
-        self.assertEqual(len(re.findall('WARNING',output)),0)
-
+        self.assertEqual(len(re.findall('ERROR', output)), 0)
+        self.assertEqual(len(re.findall('WARNING', output)), 0)
 
         # now clean up the directory
         if OPTS.purge_temp:
             if os.path.exists(out_path):
                 shutil.rmtree(out_path, ignore_errors=True)
-            self.assertEqual(os.path.exists(out_path),False)
+            self.assertEqual(os.path.exists(out_path), False)
  
         globals.end_openram()
 

compiler/tests/30_openram_front_end_test.py

@@ -51,7 +51,7 @@ class openram_front_end_test(openram_test):
             debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage")
             exe_name = "{0}/openram.py ".format(OPENRAM_HOME)
         else:
-            exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) 
+            exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME)
         config_name = "{0}/tests/configs/config_front_end.py".format(OPENRAM_HOME)
         cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name,
                                                                           out_file,
@@ -64,33 +64,32 @@ class openram_front_end_test(openram_test):
         
         # assert an error until we actually check a result
         for extension in ["v", "lef", "sp", "gds"]:
-            filename = "{0}/{1}.{2}".format(out_path,out_file,extension)
-            debug.info(1,"Checking for file: " + filename)
-            self.assertEqual(os.path.exists(filename),True)
+            filename = "{0}/{1}.{2}".format(out_path, out_file, extension)
+            debug.info(1, "Checking for file: " + filename)
+            self.assertEqual(os.path.exists(filename), True)
 
         # Make sure there is any .lib file
         import glob
         files = glob.glob('{0}/*.lib'.format(out_path))
         self.assertTrue(len(files)>0)
         
-        # Make sure there is any .html file 
+        # Make sure there is any .html file
         if os.path.exists(out_path):
             datasheets = glob.glob('{0}/*html'.format(out_path))
             self.assertTrue(len(datasheets)>0)
         
         # grep any errors from the output
-        output_log = open("{0}/output.log".format(out_path),"r")
+        output_log = open("{0}/output.log".format(out_path), "r")
         output = output_log.read()
         output_log.close()
-        self.assertEqual(len(re.findall('ERROR',output)),0)
-        self.assertEqual(len(re.findall('WARNING',output)),0)
+        self.assertEqual(len(re.findall('ERROR', output)), 0)
+        self.assertEqual(len(re.findall('WARNING', output)), 0)
 
-
-       # now clean up the directory
+        # now clean up the directory
         if OPTS.purge_temp:
             if os.path.exists(out_path):
                 shutil.rmtree(out_path, ignore_errors=True)
-            self.assertEqual(os.path.exists(out_path),False)
+            self.assertEqual(os.path.exists(out_path), False)
 
         globals.end_openram()
 

compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib

@@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){
     default_max_fanout   : 4.0 ;
     default_connection_class : universal ;
 
+    voltage_map ( VDD, 1.0 );
+    voltage_map ( GND, 0 );
+
     lu_table_template(CELL_TABLE){
         variable_1 : input_net_transition;
         variable_2 : total_output_net_capacitance;
         index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
+        index_2("5.2275e-05, 0.0002091, 0.0008364");
     }
 
     lu_table_template(CONSTRAINT_TABLE){
@@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 1124.88;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
 
     leakage_power () {
-      when : "csb0";
-      value : 0.000167;
+      value : 0.000198;
     }
-    cell_leakage_power : 0;
+    cell_leakage_power : 0.000198;
     bus(din0){
         bus_type  : data; 
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         memory_write(){ 
             address : addr0; 
             clocked_on  : clk0; 
@@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){
     bus(dout0){
         bus_type  : data; 
         direction  : output; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
+        max_capacitance : 0.0008364000000000001;  
+        min_capacitance : 5.2275000000000003e-05;  
         memory_read(){ 
             address : addr0; 
         }
@@ -138,14 +150,14 @@ cell (sram_2_16_1_freepdk45){
             related_pin : "clk0"; 
             timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
-            values("0.088, 0.088, 0.088",\
-                   "0.088, 0.088, 0.088",\
-                   "0.088, 0.088, 0.088");
+            values("0.193, 0.193, 0.194",\
+                   "0.193, 0.193, 0.194",\
+                   "0.193, 0.193, 0.194");
             }
             cell_fall(CELL_TABLE) {
-            values("0.088, 0.088, 0.088",\
-                   "0.088, 0.088, 0.088",\
-                   "0.088, 0.088, 0.088");
+            values("0.193, 0.193, 0.194",\
+                   "0.193, 0.193, 0.194",\
+                   "0.193, 0.193, 0.194");
             }
             rise_transition(CELL_TABLE) {
             values("0.001, 0.001, 0.001",\
@@ -164,7 +176,7 @@ cell (sram_2_16_1_freepdk45){
     bus(addr0){
         bus_type  : addr; 
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         max_transition       : 0.04;
         pin(addr0[3:0]){
         timing(){ 
@@ -200,7 +212,7 @@ cell (sram_2_16_1_freepdk45){
 
     pin(csb0){
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -233,7 +245,7 @@ cell (sram_2_16_1_freepdk45){
 
     pin(web0){
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){
     pin(clk0){
         clock             : true;
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         internal_power(){
-            when : "!csb0 & clk0 & !web0"; 
+            when : "!csb0 & !web0"; 
             rise_power(scalar){
-                values("0.033101244168888884");
+                values("9.240667e-02");
             }
             fall_power(scalar){
-                values("0.033101244168888884");
+                values("9.240667e-02");
             }
         }
         internal_power(){
-            when : "!csb0 & !clk0 & web0"; 
+            when : "csb0 & !web0"; 
             rise_power(scalar){
-                values("0.033101244168888884");
+                values("9.240667e-02");
             }
             fall_power(scalar){
-                values("0.033101244168888884");
+                values("9.240667e-02");
             }
         }
         internal_power(){
-            when : "csb0"; 
+            when : "!csb0 & web0"; 
             rise_power(scalar){
-                values("0");
+                values("9.240667e-02");
             }
             fall_power(scalar){
-                values("0");
+                values("9.240667e-02");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("9.240667e-02");
+            }
+            fall_power(scalar){
+                values("9.240667e-02");
             }
         }
         timing(){ 
             timing_type :"min_pulse_width"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0.009"); 
+                values("0.0195"); 
             }
             fall_constraint(scalar) {
-                values("0.009"); 
+                values("0.0195"); 
             }
          }
         timing(){ 
             timing_type :"minimum_period"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0.018"); 
+                values("0.039"); 
             }
             fall_constraint(scalar) {
-                values("0.018"); 
+                values("0.039"); 
             }
          }
     }

compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib

@@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){
     default_max_fanout   : 4.0 ;
     default_connection_class : universal ;
 
+    voltage_map ( VDD, 1.0 );
+    voltage_map ( GND, 0 );
+
     lu_table_template(CELL_TABLE){
         variable_1 : input_net_transition;
         variable_2 : total_output_net_capacitance;
         index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
+        index_2("5.2275e-05, 0.0002091, 0.0008364");
     }
 
     lu_table_template(CONSTRAINT_TABLE){
@@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 1124.88;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
 
     leakage_power () {
-      when : "csb0";
-      value : 0.000167;
+      value : 0.000198;
     }
-    cell_leakage_power : 0;
+    cell_leakage_power : 0.000198;
     bus(din0){
         bus_type  : data; 
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         memory_write(){ 
             address : addr0; 
             clocked_on  : clk0; 
@@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){
     bus(dout0){
         bus_type  : data; 
         direction  : output; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
+        max_capacitance : 0.0008364000000000001;  
+        min_capacitance : 5.2275000000000003e-05;  
         memory_read(){ 
             address : addr0; 
         }
@@ -138,14 +150,14 @@ cell (sram_2_16_1_freepdk45){
             related_pin : "clk0"; 
             timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
-            values("0.107, 0.107, 0.107",\
-                   "0.107, 0.107, 0.107",\
-                   "0.107, 0.107, 0.107");
+            values("0.236, 0.236, 0.237",\
+                   "0.236, 0.236, 0.237",\
+                   "0.236, 0.236, 0.237");
             }
             cell_fall(CELL_TABLE) {
-            values("0.107, 0.107, 0.107",\
-                   "0.107, 0.107, 0.107",\
-                   "0.107, 0.107, 0.107");
+            values("0.236, 0.236, 0.237",\
+                   "0.236, 0.236, 0.237",\
+                   "0.236, 0.236, 0.237");
             }
             rise_transition(CELL_TABLE) {
             values("0.001, 0.001, 0.001",\
@@ -164,7 +176,7 @@ cell (sram_2_16_1_freepdk45){
     bus(addr0){
         bus_type  : addr; 
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         max_transition       : 0.04;
         pin(addr0[3:0]){
         timing(){ 
@@ -200,7 +212,7 @@ cell (sram_2_16_1_freepdk45){
 
     pin(csb0){
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -233,7 +245,7 @@ cell (sram_2_16_1_freepdk45){
 
     pin(web0){
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){
     pin(clk0){
         clock             : true;
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         internal_power(){
-            when : "!csb0 & clk0 & !web0"; 
+            when : "!csb0 & !web0"; 
             rise_power(scalar){
-                values("0.033101244168888884");
+                values("7.560546e-02");
             }
             fall_power(scalar){
-                values("0.033101244168888884");
+                values("7.560546e-02");
             }
         }
         internal_power(){
-            when : "!csb0 & !clk0 & web0"; 
+            when : "csb0 & !web0"; 
             rise_power(scalar){
-                values("0.033101244168888884");
+                values("7.560546e-02");
             }
             fall_power(scalar){
-                values("0.033101244168888884");
+                values("7.560546e-02");
             }
         }
         internal_power(){
-            when : "csb0"; 
+            when : "!csb0 & web0"; 
             rise_power(scalar){
-                values("0");
+                values("7.560546e-02");
             }
             fall_power(scalar){
-                values("0");
+                values("7.560546e-02");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("7.560546e-02");
+            }
+            fall_power(scalar){
+                values("7.560546e-02");
             }
         }
         timing(){ 
             timing_type :"min_pulse_width"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0.0105"); 
+                values("0.0235"); 
             }
             fall_constraint(scalar) {
-                values("0.0105"); 
+                values("0.0235"); 
             }
          }
         timing(){ 
             timing_type :"minimum_period"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0.021"); 
+                values("0.047"); 
             }
             fall_constraint(scalar) {
-                values("0.021"); 
+                values("0.047"); 
             }
          }
     }

compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib

@@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
     default_max_fanout   : 4.0 ;
     default_connection_class : universal ;
 
+    voltage_map ( VDD, 1.0 );
+    voltage_map ( GND, 0 );
+
     lu_table_template(CELL_TABLE){
         variable_1 : input_net_transition;
         variable_2 : total_output_net_capacitance;
         index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
+        index_2("5.2275e-05, 0.0002091, 0.0008364");
     }
 
     lu_table_template(CONSTRAINT_TABLE){
@@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 977.4951374999999;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
 
     leakage_power () {
-      when : "csb0";
-      value : 0.0011164579999999999;
+      value : 0.00163;
     }
-    cell_leakage_power : 0;
+    cell_leakage_power : 0.00163;
     bus(din0){
         bus_type  : data; 
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         memory_write(){ 
             address : addr0; 
             clocked_on  : clk0; 
@@ -98,9 +110,9 @@ cell (sram_2_16_1_freepdk45){
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.033, 0.039",\
-                   "0.033, 0.033, 0.039",\
-                   "0.033, 0.033, 0.039");
+            values("0.033, 0.033, 0.033",\
+                   "0.033, 0.033, 0.033",\
+                   "0.033, 0.033, 0.033");
             }
             fall_constraint(CONSTRAINT_TABLE) {
             values("0.027, 0.027, 0.033",\
@@ -112,14 +124,14 @@ cell (sram_2_16_1_freepdk45){
             timing_type : hold_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.01, -0.016, -0.022",\
-                   "-0.01, -0.016, -0.022",\
-                   "-0.01, -0.016, -0.022");
+            values("-0.01, -0.01, 0.021",\
+                   "-0.01, -0.01, 0.021",\
+                   "-0.01, -0.01, 0.021");
               }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.016, -0.016, -0.016",\
-                   "-0.016, -0.016, -0.016",\
-                   "-0.016, -0.016, -0.016");
+            values("-0.016, -0.01, -0.016",\
+                   "-0.016, -0.01, -0.016",\
+                   "-0.016, -0.01, -0.016");
             }
         }
         }
@@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){
     bus(dout0){
         bus_type  : data; 
         direction  : output; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
+        max_capacitance : 0.0008364000000000001;  
+        min_capacitance : 5.2275000000000003e-05;  
         memory_read(){ 
             address : addr0; 
         }
@@ -138,24 +150,24 @@ cell (sram_2_16_1_freepdk45){
             related_pin : "clk0"; 
             timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
-            values("0.235, 0.235, 0.239",\
-                   "0.235, 0.236, 0.24",\
-                   "0.241, 0.242, 0.246");
+            values("0.226, 0.227, 0.232",\
+                   "0.227, 0.228, 0.233",\
+                   "0.232, 0.234, 0.238");
             }
             cell_fall(CELL_TABLE) {
-            values("2.583, 2.585, 2.612",\
-                   "2.584, 2.585, 2.613",\
-                   "2.59, 2.592, 2.62");
+            values("0.226, 0.227, 0.232",\
+                   "0.227, 0.228, 0.233",\
+                   "0.232, 0.234, 0.238");
             }
             rise_transition(CELL_TABLE) {
-            values("0.022, 0.022, 0.03",\
-                   "0.022, 0.023, 0.03",\
-                   "0.022, 0.022, 0.03");
+            values("0.256, 0.256, 0.257",\
+                   "0.256, 0.256, 0.257",\
+                   "0.256, 0.256, 0.257");
             }
             fall_transition(CELL_TABLE) {
-            values("0.078, 0.079, 0.083",\
-                   "0.078, 0.079, 0.083",\
-                   "0.079, 0.079, 0.083");
+            values("0.256, 0.256, 0.257",\
+                   "0.256, 0.256, 0.257",\
+                   "0.256, 0.256, 0.257");
             }
         }
         }
@@ -164,16 +176,16 @@ cell (sram_2_16_1_freepdk45){
     bus(addr0){
         bus_type  : addr; 
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         max_transition       : 0.04;
         pin(addr0[3:0]){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.033, 0.039",\
-                   "0.033, 0.033, 0.039",\
-                   "0.033, 0.033, 0.039");
+            values("0.033, 0.033, 0.033",\
+                   "0.033, 0.033, 0.033",\
+                   "0.033, 0.033, 0.033");
             }
             fall_constraint(CONSTRAINT_TABLE) {
             values("0.027, 0.027, 0.033",\
@@ -185,14 +197,14 @@ cell (sram_2_16_1_freepdk45){
             timing_type : hold_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.01, -0.016, -0.022",\
-                   "-0.01, -0.016, -0.022",\
-                   "-0.01, -0.016, -0.022");
+            values("-0.01, -0.01, 0.021",\
+                   "-0.01, -0.01, 0.021",\
+                   "-0.01, -0.01, 0.021");
               }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.016, -0.016, -0.016",\
-                   "-0.016, -0.016, -0.016",\
-                   "-0.016, -0.016, -0.016");
+            values("-0.016, -0.01, -0.016",\
+                   "-0.016, -0.01, -0.016",\
+                   "-0.016, -0.01, -0.016");
             }
         }
         }
@@ -200,14 +212,14 @@ cell (sram_2_16_1_freepdk45){
 
     pin(csb0){
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.033, 0.039",\
-                   "0.033, 0.033, 0.039",\
-                   "0.033, 0.033, 0.039");
+            values("0.033, 0.033, 0.033",\
+                   "0.033, 0.033, 0.033",\
+                   "0.033, 0.033, 0.033");
             }
             fall_constraint(CONSTRAINT_TABLE) {
             values("0.027, 0.027, 0.033",\
@@ -219,28 +231,28 @@ cell (sram_2_16_1_freepdk45){
             timing_type : hold_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.01, -0.016, -0.022",\
-                   "-0.01, -0.016, -0.022",\
-                   "-0.01, -0.016, -0.022");
+            values("-0.01, -0.01, 0.021",\
+                   "-0.01, -0.01, 0.021",\
+                   "-0.01, -0.01, 0.021");
               }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.016, -0.016, -0.016",\
-                   "-0.016, -0.016, -0.016",\
-                   "-0.016, -0.016, -0.016");
+            values("-0.016, -0.01, -0.016",\
+                   "-0.016, -0.01, -0.016",\
+                   "-0.016, -0.01, -0.016");
             }
         }
     }
 
     pin(web0){
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.033, 0.039",\
-                   "0.033, 0.033, 0.039",\
-                   "0.033, 0.033, 0.039");
+            values("0.033, 0.033, 0.033",\
+                   "0.033, 0.033, 0.033",\
+                   "0.033, 0.033, 0.033");
             }
             fall_constraint(CONSTRAINT_TABLE) {
             values("0.027, 0.027, 0.033",\
@@ -252,14 +264,14 @@ cell (sram_2_16_1_freepdk45){
             timing_type : hold_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.01, -0.016, -0.022",\
-                   "-0.01, -0.016, -0.022",\
-                   "-0.01, -0.016, -0.022");
+            values("-0.01, -0.01, 0.021",\
+                   "-0.01, -0.01, 0.021",\
+                   "-0.01, -0.01, 0.021");
               }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.016, -0.016, -0.016",\
-                   "-0.016, -0.016, -0.016",\
-                   "-0.016, -0.016, -0.016");
+            values("-0.016, -0.01, -0.016",\
+                   "-0.016, -0.01, -0.016",\
+                   "-0.016, -0.01, -0.016");
             }
         }
     }
@@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){
     pin(clk0){
         clock             : true;
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         internal_power(){
-            when : "!csb0 & clk0 & !web0"; 
+            when : "!csb0 & !web0"; 
             rise_power(scalar){
-                values("0.03599689694444445");
+                values("3.069977e-01");
             }
             fall_power(scalar){
-                values("0.03599689694444445");
+                values("3.686680e-01");
             }
         }
         internal_power(){
-            when : "!csb0 & !clk0 & web0"; 
+            when : "csb0 & !web0"; 
             rise_power(scalar){
-                values("0.029906643888888886");
+                values("2.055845e-01");
             }
             fall_power(scalar){
-                values("0.029906643888888886");
+                values("1.933561e-01");
             }
         }
         internal_power(){
-            when : "csb0"; 
+            when : "!csb0 & web0"; 
             rise_power(scalar){
-                values("0");
+                values("3.315565e-01");
             }
             fall_power(scalar){
-                values("0");
+                values("3.314553e-01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("1.777355e-01");
+            }
+            fall_power(scalar){
+                values("1.615044e-01");
             }
         }
         timing(){ 
             timing_type :"min_pulse_width"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("2.422"); 
+                values("0.449"); 
             }
             fall_constraint(scalar) {
-                values("2.422"); 
+                values("0.449"); 
             }
          }
         timing(){ 
             timing_type :"minimum_period"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("4.844"); 
+                values("0.898"); 
             }
             fall_constraint(scalar) {
-                values("4.844"); 
+                values("0.898"); 
             }
          }
     }

compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib

@@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
     default_max_fanout   : 4.0 ;
     default_connection_class : universal ;
 
+    voltage_map ( VDD, 1.0 );
+    voltage_map ( GND, 0 );
+
     lu_table_template(CELL_TABLE){
         variable_1 : input_net_transition;
         variable_2 : total_output_net_capacitance;
         index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
+        index_2("5.2275e-05, 0.0002091, 0.0008364");
     }
 
     lu_table_template(CONSTRAINT_TABLE){
@@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 977.4951374999999;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
 
     leakage_power () {
-      when : "csb0";
-      value : 0.000179;
+      value : 0.000198;
     }
-    cell_leakage_power : 0;
+    cell_leakage_power : 0.000198;
     bus(din0){
         bus_type  : data; 
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         memory_write(){ 
             address : addr0; 
             clocked_on  : clk0; 
@@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){
     bus(dout0){
         bus_type  : data; 
         direction  : output; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
+        max_capacitance : 0.0008364000000000001;  
+        min_capacitance : 5.2275000000000003e-05;  
         memory_read(){ 
             address : addr0; 
         }
@@ -138,14 +150,14 @@ cell (sram_2_16_1_freepdk45){
             related_pin : "clk0"; 
             timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
-            values("0.098, 0.098, 0.098",\
-                   "0.098, 0.098, 0.098",\
-                   "0.098, 0.098, 0.098");
+            values("0.215, 0.215, 0.216",\
+                   "0.215, 0.215, 0.216",\
+                   "0.215, 0.215, 0.216");
             }
             cell_fall(CELL_TABLE) {
-            values("0.098, 0.098, 0.098",\
-                   "0.098, 0.098, 0.098",\
-                   "0.098, 0.098, 0.098");
+            values("0.215, 0.215, 0.216",\
+                   "0.215, 0.215, 0.216",\
+                   "0.215, 0.215, 0.216");
             }
             rise_transition(CELL_TABLE) {
             values("0.001, 0.001, 0.001",\
@@ -164,7 +176,7 @@ cell (sram_2_16_1_freepdk45){
     bus(addr0){
         bus_type  : addr; 
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         max_transition       : 0.04;
         pin(addr0[3:0]){
         timing(){ 
@@ -200,7 +212,7 @@ cell (sram_2_16_1_freepdk45){
 
     pin(csb0){
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -233,7 +245,7 @@ cell (sram_2_16_1_freepdk45){
 
     pin(web0){
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){
     pin(clk0){
         clock             : true;
         direction  : input; 
-        capacitance : 0.2091;  
+        capacitance : 0.00020910000000000001;  
         internal_power(){
-            when : "!csb0 & clk0 & !web0"; 
+            when : "!csb0 & !web0"; 
             rise_power(scalar){
-                values("0.0747594982142222");
+                values("8.316600e-02");
             }
             fall_power(scalar){
-                values("0.0747594982142222");
+                values("8.316600e-02");
             }
         }
         internal_power(){
-            when : "!csb0 & !clk0 & web0"; 
+            when : "csb0 & !web0"; 
             rise_power(scalar){
-                values("0.0747594982142222");
+                values("8.316600e-02");
             }
             fall_power(scalar){
-                values("0.0747594982142222");
+                values("8.316600e-02");
             }
         }
         internal_power(){
-            when : "csb0"; 
+            when : "!csb0 & web0"; 
             rise_power(scalar){
-                values("0");
+                values("8.316600e-02");
             }
             fall_power(scalar){
-                values("0");
+                values("8.316600e-02");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("8.316600e-02");
+            }
+            fall_power(scalar){
+                values("8.316600e-02");
             }
         }
         timing(){ 
             timing_type :"min_pulse_width"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0.0"); 
+                values("0.0215"); 
             }
             fall_constraint(scalar) {
-                values("0.0"); 
+                values("0.0215"); 
             }
          }
         timing(){ 
             timing_type :"minimum_period"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0"); 
+                values("0.043"); 
             }
             fall_constraint(scalar) {
-                values("0"); 
+                values("0.043"); 
             }
          }
     }

compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib

@@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){
     default_max_fanout   : 4.0 ;
     default_connection_class : universal ;
 
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
     lu_table_template(CELL_TABLE){
         variable_1 : input_net_transition;
         variable_2 : total_output_net_capacitance;
         index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
+        index_2("0.00245605, 0.0098242, 0.0392968");
     }
 
     lu_table_template(CONSTRAINT_TABLE){
@@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 73068.14000000001;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
 
     leakage_power () {
-      when : "csb0";
-      value : 0.000167;
+      value : 0.000198;
     }
-    cell_leakage_power : 0;
+    cell_leakage_power : 0.000198;
     bus(din0){
         bus_type  : data; 
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         memory_write(){ 
             address : addr0; 
             clocked_on  : clk0; 
@@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){
     bus(dout0){
         bus_type  : data; 
         direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
         memory_read(){ 
             address : addr0; 
         }
@@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){
             related_pin : "clk0"; 
             timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
-            values("0.241, 0.241, 0.241",\
-                   "0.241, 0.241, 0.241",\
-                   "0.241, 0.241, 0.241");
+            values("1.183, 1.199, 1.264",\
+                   "1.183, 1.199, 1.264",\
+                   "1.183, 1.199, 1.264");
             }
             cell_fall(CELL_TABLE) {
-            values("0.241, 0.241, 0.241",\
-                   "0.241, 0.241, 0.241",\
-                   "0.241, 0.241, 0.241");
+            values("1.183, 1.199, 1.264",\
+                   "1.183, 1.199, 1.264",\
+                   "1.183, 1.199, 1.264");
             }
             rise_transition(CELL_TABLE) {
-            values("0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004");
+            values("0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014");
             }
             fall_transition(CELL_TABLE) {
-            values("0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004");
+            values("0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014");
             }
         }
         }
@@ -164,7 +176,7 @@ cell (sram_2_16_1_scn4m_subm){
     bus(addr0){
         bus_type  : addr; 
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         max_transition       : 0.4;
         pin(addr0[3:0]){
         timing(){ 
@@ -200,7 +212,7 @@ cell (sram_2_16_1_scn4m_subm){
 
     pin(csb0){
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -233,7 +245,7 @@ cell (sram_2_16_1_scn4m_subm){
 
     pin(web0){
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){
     pin(clk0){
         clock             : true;
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         internal_power(){
-            when : "!csb0 & clk0 & !web0"; 
+            when : "!csb0 & !web0"; 
             rise_power(scalar){
-                values("4.99880645");
+                values("7.797263e+00");
             }
             fall_power(scalar){
-                values("4.99880645");
+                values("7.797263e+00");
             }
         }
         internal_power(){
-            when : "!csb0 & !clk0 & web0"; 
+            when : "csb0 & !web0"; 
             rise_power(scalar){
-                values("4.99880645");
+                values("7.797263e+00");
             }
             fall_power(scalar){
-                values("4.99880645");
+                values("7.797263e+00");
             }
         }
         internal_power(){
-            when : "csb0"; 
+            when : "!csb0 & web0"; 
             rise_power(scalar){
-                values("0");
+                values("7.797263e+00");
             }
             fall_power(scalar){
-                values("0");
+                values("7.797263e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("7.797263e+00");
+            }
+            fall_power(scalar){
+                values("7.797263e+00");
             }
         }
         timing(){ 
             timing_type :"min_pulse_width"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0.024"); 
+                values("0.1265"); 
             }
             fall_constraint(scalar) {
-                values("0.024"); 
+                values("0.1265"); 
             }
          }
         timing(){ 
             timing_type :"minimum_period"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0.048"); 
+                values("0.253"); 
             }
             fall_constraint(scalar) {
-                values("0.048"); 
+                values("0.253"); 
             }
          }
     }

compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib

@@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){
     default_max_fanout   : 4.0 ;
     default_connection_class : universal ;
 
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
     lu_table_template(CELL_TABLE){
         variable_1 : input_net_transition;
         variable_2 : total_output_net_capacitance;
         index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
+        index_2("0.00245605, 0.0098242, 0.0392968");
     }
 
     lu_table_template(CONSTRAINT_TABLE){
@@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 73068.14000000001;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
 
     leakage_power () {
-      when : "csb0";
-      value : 0.000167;
+      value : 0.000198;
     }
-    cell_leakage_power : 0;
+    cell_leakage_power : 0.000198;
     bus(din0){
         bus_type  : data; 
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         memory_write(){ 
             address : addr0; 
             clocked_on  : clk0; 
@@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){
     bus(dout0){
         bus_type  : data; 
         direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
         memory_read(){ 
             address : addr0; 
         }
@@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){
             related_pin : "clk0"; 
             timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
-            values("0.294, 0.294, 0.294",\
-                   "0.294, 0.294, 0.294",\
-                   "0.294, 0.294, 0.294");
+            values("1.446, 1.466, 1.545",\
+                   "1.446, 1.466, 1.545",\
+                   "1.446, 1.466, 1.545");
             }
             cell_fall(CELL_TABLE) {
-            values("0.294, 0.294, 0.294",\
-                   "0.294, 0.294, 0.294",\
-                   "0.294, 0.294, 0.294");
+            values("1.446, 1.466, 1.545",\
+                   "1.446, 1.466, 1.545",\
+                   "1.446, 1.466, 1.545");
             }
             rise_transition(CELL_TABLE) {
-            values("0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004");
+            values("0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017");
             }
             fall_transition(CELL_TABLE) {
-            values("0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004");
+            values("0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017");
             }
         }
         }
@@ -164,7 +176,7 @@ cell (sram_2_16_1_scn4m_subm){
     bus(addr0){
         bus_type  : addr; 
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         max_transition       : 0.4;
         pin(addr0[3:0]){
         timing(){ 
@@ -200,7 +212,7 @@ cell (sram_2_16_1_scn4m_subm){
 
     pin(csb0){
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -233,7 +245,7 @@ cell (sram_2_16_1_scn4m_subm){
 
     pin(web0){
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){
     pin(clk0){
         clock             : true;
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         internal_power(){
-            when : "!csb0 & clk0 & !web0"; 
+            when : "!csb0 & !web0"; 
             rise_power(scalar){
-                values("4.99880645");
+                values("6.379579e+00");
             }
             fall_power(scalar){
-                values("4.99880645");
+                values("6.379579e+00");
             }
         }
         internal_power(){
-            when : "!csb0 & !clk0 & web0"; 
+            when : "csb0 & !web0"; 
             rise_power(scalar){
-                values("4.99880645");
+                values("6.379579e+00");
             }
             fall_power(scalar){
-                values("4.99880645");
+                values("6.379579e+00");
             }
         }
         internal_power(){
-            when : "csb0"; 
+            when : "!csb0 & web0"; 
             rise_power(scalar){
-                values("0");
+                values("6.379579e+00");
             }
             fall_power(scalar){
-                values("0");
+                values("6.379579e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("6.379579e+00");
+            }
+            fall_power(scalar){
+                values("6.379579e+00");
             }
         }
         timing(){ 
             timing_type :"min_pulse_width"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0.0295"); 
+                values("0.1545"); 
             }
             fall_constraint(scalar) {
-                values("0.0295"); 
+                values("0.1545"); 
             }
          }
         timing(){ 
             timing_type :"minimum_period"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0.059"); 
+                values("0.309"); 
             }
             fall_constraint(scalar) {
-                values("0.059"); 
+                values("0.309"); 
             }
          }
     }

compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib

@@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
     default_max_fanout   : 4.0 ;
     default_connection_class : universal ;
 
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
     lu_table_template(CELL_TABLE){
         variable_1 : input_net_transition;
         variable_2 : total_output_net_capacitance;
         index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
+        index_2("0.00245605, 0.0098242, 0.0392968");
     }
 
     lu_table_template(CONSTRAINT_TABLE){
@@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 60774.3;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
 
     leakage_power () {
-      when : "csb0";
-      value : 0.0009813788999999999;
+      value : 0.000198;
     }
-    cell_leakage_power : 0;
+    cell_leakage_power : 0.000198;
     bus(din0){
         bus_type  : data; 
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         memory_write(){ 
             address : addr0; 
             clocked_on  : clk0; 
@@ -98,28 +110,28 @@ cell (sram_2_16_1_scn4m_subm){
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("0.167, 0.167, 0.228",\
-                   "0.167, 0.167, 0.228",\
-                   "0.167, 0.167, 0.228");
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
             }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("0.131, 0.125, 0.137",\
-                   "0.131, 0.125, 0.137",\
-                   "0.131, 0.125, 0.137");
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
             }
         }
         timing(){ 
             timing_type : hold_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.065, -0.071, -0.114",\
-                   "-0.065, -0.071, -0.114",\
-                   "-0.065, -0.071, -0.114");
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
               }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.089, -0.089, -0.089",\
-                   "-0.089, -0.089, -0.089",\
-                   "-0.089, -0.089, -0.089");
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
             }
         }
         }
@@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){
     bus(dout0){
         bus_type  : data; 
         direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
         memory_read(){ 
             address : addr0; 
         }
@@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){
             related_pin : "clk0"; 
             timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
-            values("1.556, 1.576, 1.751",\
-                   "1.559, 1.579, 1.754",\
-                   "1.624, 1.643, 1.819");
+            values("1.314, 1.332, 1.404",\
+                   "1.314, 1.332, 1.404",\
+                   "1.314, 1.332, 1.404");
             }
             cell_fall(CELL_TABLE) {
-            values("3.445, 3.504, 3.926",\
-                   "3.448, 3.507, 3.93",\
-                   "3.49, 3.549, 3.972");
+            values("1.314, 1.332, 1.404",\
+                   "1.314, 1.332, 1.404",\
+                   "1.314, 1.332, 1.404");
             }
             rise_transition(CELL_TABLE) {
-            values("0.13, 0.169, 0.574",\
-                   "0.13, 0.169, 0.574",\
-                   "0.13, 0.169, 0.574");
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
             }
             fall_transition(CELL_TABLE) {
-            values("0.467, 0.49, 0.959",\
-                   "0.467, 0.49, 0.959",\
-                   "0.47, 0.493, 0.96");
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
             }
         }
         }
@@ -164,35 +176,35 @@ cell (sram_2_16_1_scn4m_subm){
     bus(addr0){
         bus_type  : addr; 
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         max_transition       : 0.4;
         pin(addr0[3:0]){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("0.167, 0.167, 0.228",\
-                   "0.167, 0.167, 0.228",\
-                   "0.167, 0.167, 0.228");
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
             }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("0.131, 0.125, 0.137",\
-                   "0.131, 0.125, 0.137",\
-                   "0.131, 0.125, 0.137");
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
             }
         }
         timing(){ 
             timing_type : hold_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.065, -0.071, -0.114",\
-                   "-0.065, -0.071, -0.114",\
-                   "-0.065, -0.071, -0.114");
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
               }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.089, -0.089, -0.089",\
-                   "-0.089, -0.089, -0.089",\
-                   "-0.089, -0.089, -0.089");
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
             }
         }
         }
@@ -200,66 +212,66 @@ cell (sram_2_16_1_scn4m_subm){
 
     pin(csb0){
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("0.167, 0.167, 0.228",\
-                   "0.167, 0.167, 0.228",\
-                   "0.167, 0.167, 0.228");
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
             }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("0.131, 0.125, 0.137",\
-                   "0.131, 0.125, 0.137",\
-                   "0.131, 0.125, 0.137");
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
             }
         }
         timing(){ 
             timing_type : hold_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.065, -0.071, -0.114",\
-                   "-0.065, -0.071, -0.114",\
-                   "-0.065, -0.071, -0.114");
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
               }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.089, -0.089, -0.089",\
-                   "-0.089, -0.089, -0.089",\
-                   "-0.089, -0.089, -0.089");
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
             }
         }
     }
 
     pin(web0){
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("0.167, 0.167, 0.228",\
-                   "0.167, 0.167, 0.228",\
-                   "0.167, 0.167, 0.228");
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
             }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("0.131, 0.125, 0.137",\
-                   "0.131, 0.125, 0.137",\
-                   "0.131, 0.125, 0.137");
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
             }
         }
         timing(){ 
             timing_type : hold_rising; 
             related_pin  : "clk0"; 
             rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.065, -0.071, -0.114",\
-                   "-0.065, -0.071, -0.114",\
-                   "-0.065, -0.071, -0.114");
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
               }
             fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.089, -0.089, -0.089",\
-                   "-0.089, -0.089, -0.089",\
-                   "-0.089, -0.089, -0.089");
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
             }
         }
     }
@@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){
     pin(clk0){
         clock             : true;
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         internal_power(){
-            when : "!csb0 & clk0 & !web0"; 
+            when : "!csb0 & !web0"; 
             rise_power(scalar){
-                values("9.972790277777777");
+                values("7.017537e+00");
             }
             fall_power(scalar){
-                values("9.972790277777777");
+                values("7.017537e+00");
             }
         }
         internal_power(){
-            when : "!csb0 & !clk0 & web0"; 
+            when : "csb0 & !web0"; 
             rise_power(scalar){
-                values("8.899322499999998");
+                values("7.017537e+00");
             }
             fall_power(scalar){
-                values("8.899322499999998");
+                values("7.017537e+00");
             }
         }
         internal_power(){
-            when : "csb0"; 
+            when : "!csb0 & web0"; 
             rise_power(scalar){
-                values("0");
+                values("7.017537e+00");
             }
             fall_power(scalar){
-                values("0");
+                values("7.017537e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("7.017537e+00");
+            }
+            fall_power(scalar){
+                values("7.017537e+00");
             }
         }
         timing(){ 
             timing_type :"min_pulse_width"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("2.344"); 
+                values("0.1405"); 
             }
             fall_constraint(scalar) {
-                values("2.344"); 
+                values("0.1405"); 
             }
          }
         timing(){ 
             timing_type :"minimum_period"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("4.688"); 
+                values("0.281"); 
             }
             fall_constraint(scalar) {
-                values("4.688"); 
+                values("0.281"); 
             }
          }
     }

compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib

@@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
     default_max_fanout   : 4.0 ;
     default_connection_class : universal ;
 
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
     lu_table_template(CELL_TABLE){
         variable_1 : input_net_transition;
         variable_2 : total_output_net_capacitance;
         index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
+        index_2("0.00245605, 0.0098242, 0.0392968");
     }
 
     lu_table_template(CONSTRAINT_TABLE){
@@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){
     dont_use  : true;
     map_only   : true;
     dont_touch : true;
-    area : 60774.3;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
 
     leakage_power () {
-      when : "csb0";
-      value : 0.000179;
+      value : 0.000198;
     }
-    cell_leakage_power : 0;
+    cell_leakage_power : 0.000198;
     bus(din0){
         bus_type  : data; 
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         memory_write(){ 
             address : addr0; 
             clocked_on  : clk0; 
@@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){
     bus(dout0){
         bus_type  : data; 
         direction  : output; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
         memory_read(){ 
             address : addr0; 
         }
@@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){
             related_pin : "clk0"; 
             timing_type : falling_edge; 
             cell_rise(CELL_TABLE) {
-            values("0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268");
+            values("1.314, 1.332, 1.404",\
+                   "1.314, 1.332, 1.404",\
+                   "1.314, 1.332, 1.404");
             }
             cell_fall(CELL_TABLE) {
-            values("0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268",\
-                   "0.268, 0.268, 0.268");
+            values("1.314, 1.332, 1.404",\
+                   "1.314, 1.332, 1.404",\
+                   "1.314, 1.332, 1.404");
             }
             rise_transition(CELL_TABLE) {
-            values("0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004");
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
             }
             fall_transition(CELL_TABLE) {
-            values("0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004",\
-                   "0.004, 0.004, 0.004");
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
             }
         }
         }
@@ -164,7 +176,7 @@ cell (sram_2_16_1_scn4m_subm){
     bus(addr0){
         bus_type  : addr; 
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         max_transition       : 0.4;
         pin(addr0[3:0]){
         timing(){ 
@@ -200,7 +212,7 @@ cell (sram_2_16_1_scn4m_subm){
 
     pin(csb0){
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -233,7 +245,7 @@ cell (sram_2_16_1_scn4m_subm){
 
     pin(web0){
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){
     pin(clk0){
         clock             : true;
         direction  : input; 
-        capacitance : 9.8242;  
+        capacitance : 0.0098242;  
         internal_power(){
-            when : "!csb0 & clk0 & !web0"; 
+            when : "!csb0 & !web0"; 
             rise_power(scalar){
-                values("11.3049604371");
+                values("7.017537e+00");
             }
             fall_power(scalar){
-                values("11.3049604371");
+                values("7.017537e+00");
             }
         }
         internal_power(){
-            when : "!csb0 & !clk0 & web0"; 
+            when : "csb0 & !web0"; 
             rise_power(scalar){
-                values("11.3049604371");
+                values("7.017537e+00");
             }
             fall_power(scalar){
-                values("11.3049604371");
+                values("7.017537e+00");
             }
         }
         internal_power(){
-            when : "csb0"; 
+            when : "!csb0 & web0"; 
             rise_power(scalar){
-                values("0");
+                values("7.017537e+00");
             }
             fall_power(scalar){
-                values("0");
+                values("7.017537e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("7.017537e+00");
+            }
+            fall_power(scalar){
+                values("7.017537e+00");
             }
         }
         timing(){ 
             timing_type :"min_pulse_width"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0.0"); 
+                values("0.1405"); 
             }
             fall_constraint(scalar) {
-                values("0.0"); 
+                values("0.1405"); 
             }
          }
         timing(){ 
             timing_type :"minimum_period"; 
             related_pin  : clk0; 
             rise_constraint(scalar) {
-                values("0"); 
+                values("0.281"); 
             }
             fall_constraint(scalar) {
-                values("0"); 
+                values("0.281"); 
             }
          }
     }

compiler/tests/testutils.py

@@ -39,27 +39,40 @@ class openram_test(unittest.TestCase):
         tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name)
         tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name)
 
-        a.sp_write(tempspice)
+        a.lvs_write(tempspice)
         # cannot write gds in netlist_only mode
         if not OPTS.netlist_only:
             a.gds_write(tempgds)
 
             import verify
-            result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification)
-            if result != 0:
+            # Run both DRC and LVS even if DRC might fail
+            # Magic can still extract despite DRC failing, so it might be ok in some techs
+            # if we ignore things like minimum metal area of pins
+            drc_result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification)
+
+            # Always run LVS if we are using magic
+            if "magic" in OPTS.drc_exe or drc_result == 0:
+                lvs_result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification)
+                
+            # Only allow DRC to fail and LVS to pass if we are using magic
+            if "magic" in OPTS.drc_exe and lvs_result == 0 and drc_result != 0:
+                #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
+                #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
+                #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
+                debug.warning("DRC failed but LVS passed: {}".format(a.name))
+            elif drc_result != 0:
                 #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
                 #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
                 #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
                 self.fail("DRC failed: {}".format(a.name))
-
-
-            result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification)
-            if result != 0:
+                
+            if lvs_result != 0:
                 #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
                 #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
                 #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
                 self.fail("LVS mismatch: {}".format(a.name))
 
+
         # For debug...
         #import pdb; pdb.set_trace()
         if OPTS.purge_temp: