mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-30 01:48:33 +02:00
Merge branch 'dev' into bisr
This commit is contained in:
Aditi Sinha
@@ -5,14 +5,13 @@
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
from math import log
|
||||
import design
|
||||
from tech import drc
|
||||
import debug
|
||||
from sram_factory import factory
|
||||
from vector import vector
|
||||
from globals import OPTS
|
||||
|
||||
|
||||
class write_driver_array(design.design):
|
||||
"""
|
||||
Array of tristate drivers to write to the bitlines through the column mux.
|
||||
@@ -23,7 +22,7 @@ class write_driver_array(design.design):
|
||||
design.design.__init__(self, name)
|
||||
debug.info(1, "Creating {0}".format(self.name))
|
||||
self.add_comment("columns: {0}".format(columns))
|
||||
self.add_comment("word_size {0}".format(word_size))
|
||||
self.add_comment("word_size {0}".format(word_size))
|
||||
|
||||
self.columns = columns
|
||||
self.word_size = word_size
|
||||
@@ -35,7 +34,7 @@ class write_driver_array(design.design):
|
||||
self.num_spare_cols = num_spare_cols
|
||||
|
||||
if self.write_size:
|
||||
self.num_wmasks = int(self.word_size/self.write_size)
|
||||
self.num_wmasks = int(self.word_size / self.write_size)
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
@@ -61,9 +60,9 @@ class write_driver_array(design.design):
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_write_array()
|
||||
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
|
||||
if self.bitcell.width > self.driver.width:
|
||||
self.width = (self.columns + self.num_spare_cols) * self.bitcell.width
|
||||
self.width_regular_cols = self.columns * self.bitcell.width
|
||||
@@ -73,7 +72,7 @@ class write_driver_array(design.design):
|
||||
self.width_regular_cols = self.columns * self.driver.width
|
||||
self.single_col_width = self.driver.width
|
||||
self.height = self.driver.height
|
||||
|
||||
|
||||
self.place_write_array()
|
||||
self.add_layout_pins()
|
||||
self.add_boundary()
|
||||
@@ -108,9 +107,9 @@ class write_driver_array(design.design):
|
||||
self.driver_insts = {}
|
||||
w = 0
|
||||
windex=0
|
||||
for i in range(0,self.columns,self.words_per_row):
|
||||
for i in range(0, self.columns, self.words_per_row):
|
||||
name = "write_driver{}".format(i)
|
||||
index = int(i/self.words_per_row)
|
||||
index = int(i / self.words_per_row)
|
||||
self.driver_insts[index]=self.add_inst(name=name,
|
||||
mod=self.driver)
|
||||
|
||||
@@ -155,8 +154,8 @@ class write_driver_array(design.design):
|
||||
self.driver_spacing = self.bitcell.width
|
||||
else:
|
||||
self.driver_spacing = self.driver.width
|
||||
for i in range(0,self.columns,self.words_per_row):
|
||||
index = int(i/self.words_per_row)
|
||||
for i in range(0, self.columns, self.words_per_row):
|
||||
index = int(i / self.words_per_row)
|
||||
xoffset = i * self.driver_spacing
|
||||
|
||||
if cell_properties.bitcell.mirror.y and i % 2:
|
||||
@@ -182,26 +181,25 @@ class write_driver_array(design.design):
|
||||
base = vector(xoffset, 0)
|
||||
self.driver_insts[index].place(offset=base, mirror=mirror)
|
||||
|
||||
|
||||
def add_layout_pins(self):
|
||||
for i in range(self.word_size + self.num_spare_cols):
|
||||
inst = self.driver_insts[i]
|
||||
din_pin = inst.get_pin(inst.mod.din_name)
|
||||
self.add_layout_pin(text=self.data_name + "_{0}".format(i),
|
||||
layer="m2",
|
||||
layer=din_pin.layer,
|
||||
offset=din_pin.ll(),
|
||||
width=din_pin.width(),
|
||||
height=din_pin.height())
|
||||
bl_pin = inst.get_pin(inst.mod.get_bl_names())
|
||||
self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
|
||||
layer="m2",
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll(),
|
||||
width=bl_pin.width(),
|
||||
height=bl_pin.height())
|
||||
|
||||
br_pin = inst.get_pin(inst.mod.get_br_names())
|
||||
self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
|
||||
layer="m2",
|
||||
layer=br_pin.layer,
|
||||
offset=br_pin.ll(),
|
||||
width=br_pin.width(),
|
||||
height=br_pin.height())
|
||||
@@ -209,16 +207,16 @@ class write_driver_array(design.design):
|
||||
for n in ["vdd", "gnd"]:
|
||||
pin_list = self.driver_insts[i].get_pins(n)
|
||||
for pin in pin_list:
|
||||
self.add_power_pin(name = n,
|
||||
loc = pin.center(),
|
||||
self.add_power_pin(name=n,
|
||||
loc=pin.center(),
|
||||
vertical=True,
|
||||
start_layer = "m2")
|
||||
start_layer=pin.layer)
|
||||
if self.write_size:
|
||||
for bit in range(self.num_wmasks):
|
||||
inst = self.driver_insts[bit*self.write_size]
|
||||
inst = self.driver_insts[bit * self.write_size]
|
||||
en_pin = inst.get_pin(inst.mod.en_name)
|
||||
# Determine width of wmask modified en_pin with/without col mux
|
||||
wmask_en_len = self.words_per_row*(self.write_size * self.driver_spacing)
|
||||
wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
|
||||
if (self.words_per_row == 1):
|
||||
en_gap = self.driver_spacing - en_pin.width()
|
||||
else:
|
||||
@@ -227,7 +225,7 @@ class write_driver_array(design.design):
|
||||
self.add_layout_pin(text=self.en_name + "_{0}".format(bit),
|
||||
layer=en_pin.layer,
|
||||
offset=en_pin.ll(),
|
||||
width=wmask_en_len-en_gap,
|
||||
width=wmask_en_len - en_gap,
|
||||
height=en_pin.height())
|
||||
|
||||
elif self.num_spare_cols:
|
||||
@@ -250,11 +248,10 @@ class write_driver_array(design.design):
|
||||
inst = self.driver_insts[0]
|
||||
self.add_layout_pin(text=self.en_name,
|
||||
layer="m1",
|
||||
offset=inst.get_pin(inst.mod.en_name).ll().scale(0,1),
|
||||
offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1),
|
||||
width=self.width)
|
||||
|
||||
|
||||
def get_w_en_cin(self):
|
||||
"""Get the relative capacitance of all the enable connections in the bank"""
|
||||
#The enable is connected to a nand2 for every row.
|
||||
# The enable is connected to a nand2 for every row.
|
||||
return self.driver.get_w_en_cin() * len(self.driver_insts)
|
||||
|
||||
Reference in New Issue
Block a user