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https://github.com/VLSIDA/OpenRAM.git
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Merge branch 'dev' into bisr
This commit is contained in:
Aditi Sinha
@@ -13,6 +13,7 @@ import debug
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from globals import OPTS
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import logical_effort
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class sense_amp_array(design.design):
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"""
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Array of sense amplifiers to read the bitlines through the column mux.
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@@ -22,7 +23,7 @@ class sense_amp_array(design.design):
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def __init__(self, name, word_size, words_per_row, num_spare_cols=None):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("words_per_row: {0}".format(words_per_row))
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self.word_size = word_size
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@@ -60,7 +61,7 @@ class sense_amp_array(design.design):
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def create_layout(self):
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self.height = self.amp.height
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if self.bitcell.width > self.amp.width:
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self.width = self.bitcell.width * (self.word_size * self.words_per_row + self.num_spare_cols)
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else:
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@@ -80,16 +81,16 @@ class sense_amp_array(design.design):
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self.add_pin(self.en_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.amp = factory.create(module_type="sense_amp")
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self.add_mod(self.amp)
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# This is just used for measurements,
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# so don't add the module
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self.bitcell = factory.create(module_type="bitcell")
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def create_sense_amp_array(self):
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self.local_insts = []
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for i in range(0,self.word_size + self.num_spare_cols):
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@@ -110,7 +111,7 @@ class sense_amp_array(design.design):
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amp_spacing = self.amp.width * self.words_per_row
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spare_cols_spacing = self.amp.width
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for i in range(0,self.word_size):
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for i in range(0, self.word_size):
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xoffset = amp_spacing * i
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# align the xoffset to the grid of bitcells. This way we
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# know when to do the mirroring.
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@@ -142,19 +143,20 @@ class sense_amp_array(design.design):
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amp_position = vector(xoffset, 0)
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self.local_insts[index].place(offset=amp_position,mirror=mirror)
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def add_layout_pins(self):
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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self.add_power_pin(name = "gnd",
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loc = inst.get_pin("gnd").center(),
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start_layer="m2",
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vertical=True)
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self.add_power_pin(name = "vdd",
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loc = inst.get_pin("vdd").center(),
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start_layer="m2",
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gnd_pin = inst.get_pin("gnd")
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self.add_power_pin(name="gnd",
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loc=gnd_pin.center(),
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start_layer=gnd_pin.layer,
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vertical=True)
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vdd_pin = inst.get_pin("vdd")
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self.add_power_pin(name="vdd",
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loc=vdd_pin.center(),
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start_layer=vdd_pin.layer,
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vertical=True)
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bl_pin = inst.get_pin(inst.mod.get_bl_names())
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@@ -162,43 +164,43 @@ class sense_amp_array(design.design):
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dout_pin = inst.get_pin(inst.mod.dout_name)
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self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
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layer="m2",
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=bl_pin.height())
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self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
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layer="m2",
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layer=br_pin.layer,
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offset=br_pin.ll(),
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width=br_pin.width(),
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height=br_pin.height())
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self.add_layout_pin(text=self.data_name + "_{0}".format(i),
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layer="m2",
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layer=dout_pin.layer,
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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height=dout_pin.height())
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def route_rails(self):
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# add sclk rail across entire array
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sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1)
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sclk = self.amp.get_pin(self.amp.en_name)
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sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0, 1)
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self.add_layout_pin(text=self.en_name,
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layer="m1",
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offset=sclk_offset,
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width=self.width,
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height=drc("minwidth_m1"))
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layer=sclk.layer,
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offset=sclk_offset,
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width=self.width,
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height=drc("minwidth_" + sclk.layer))
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def input_load(self):
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return self.amp.input_load()
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def get_en_cin(self):
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"""Get the relative capacitance of all the sense amp enable connections in the array"""
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sense_amp_en_cin = self.amp.get_en_cin()
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return sense_amp_en_cin * (self.word_size + self.num_spare_cols)
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return sense_amp_en_cin * self.word_size
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def get_drain_cin(self):
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"""Get the relative capacitance of the drain of the PMOS isolation TX"""
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from tech import parameter
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#Bitcell drain load being used to estimate PMOS drain load
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# Bitcell drain load being used to estimate PMOS drain load
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drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
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return drain_load
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