Merge branch 'dev' into add_wmask

compiler/modules/bank.py

@@ -405,18 +405,17 @@ class bank(design.design):
     def add_modules(self):
         """ Add all the modules using the class loader """
         
-
-        self.bitcell_array = factory.create(module_type="bitcell_array",
-                                            cols=self.num_cols,
-                                            rows=self.num_rows)
-        self.add_mod(self.bitcell_array)
-        
         # create arrays of bitline and bitline_bar names for read, write, or all ports
         self.bitcell = factory.create(module_type="bitcell") 
         self.bl_names = self.bitcell.list_all_bl_names()
         self.br_names = self.bitcell.list_all_br_names()
         self.wl_names = self.bitcell.list_all_wl_names()
         self.bitline_names = self.bitcell.list_all_bitline_names()
+        
+        self.bitcell_array = factory.create(module_type="bitcell_array",
+                                            cols=self.num_cols,
+                                            rows=self.num_rows)
+        self.add_mod(self.bitcell_array)
 
         self.precharge_array = []
         for port in self.all_ports:
@@ -1285,3 +1284,13 @@ class bank(design.design):
         """Get the relative capacitance of all the sense amp enable connections in the bank"""
         #Current bank only uses sen as an enable for the sense amps.
         return self.sense_amp_array.get_en_cin()
+        
+    def graph_exclude_precharge(self):
+        """Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
+        for inst in self.precharge_array_inst:
+            if inst != None:
+                self.graph_inst_exclude.add(inst)
+                
+    def get_cell_name(self, inst_name, row, col):
+        """Gets the spice name of the target bitcell."""
+        return self.bitcell_array_inst.mod.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col)            

compiler/modules/bitcell_array.py

@@ -156,7 +156,7 @@ class bitcell_array(design.design):
         # Dynamic Power from Bitline
         bl_wire = self.gen_bl_wire()
         cell_load = 2 * bl_wire.return_input_cap() 
-        bl_swing = parameter["rbl_height_percentage"]
+        bl_swing = OPTS.rbl_delay_percentage
         freq = spice["default_event_rate"]
         bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
         
@@ -202,3 +202,16 @@ class bitcell_array(design.design):
         bitcell_wl_cin = self.cell.get_wl_cin()
         total_cin = bitcell_wl_cin * self.column_size
         return total_cin
+        
+    def graph_exclude_bits(self, targ_row, targ_col):
+        """Excludes bits in column from being added to graph except target"""
+        #Function is not robust with column mux configurations
+        for row in range(self.row_size):
+            for col in range(self.column_size):
+                if row == targ_row and col == targ_col:
+                    continue
+                self.graph_inst_exclude.add(self.cell_inst[row,col])
+            
+    def get_cell_name(self, inst_name, row, col):
+        """Gets the spice name of the target bitcell.""" 
+        return inst_name+'.x'+self.cell_inst[row,col].name, self.cell_inst[row,col]

compiler/modules/control_logic.py

@@ -144,10 +144,10 @@ class control_logic(design.design):
             self.delay_chain_resized = False
             c = reload(__import__(OPTS.replica_bitline))
             replica_bitline = getattr(c, OPTS.replica_bitline)
-            bitcell_loads = int(math.ceil(self.num_rows * parameter["rbl_height_percentage"]))
+            bitcell_loads = int(math.ceil(self.num_rows * OPTS.rbl_delay_percentage))
             #Use a model to determine the delays with that heuristic
             if OPTS.use_tech_delay_chain_size: #Use tech parameters if set.
-                fanout_list = parameter["static_fanout_list"]
+                fanout_list = OPTS.delay_chain_stages*[OPTS.delay_chain_fanout_per_stage]
                 debug.info(1, "Using tech parameters to size delay chain: fanout_list={}".format(fanout_list))
                 self.replica_bitline = factory.create(module_type="replica_bitline",
                                                       delay_fanout_list=fanout_list,
@@ -971,3 +971,7 @@ class control_logic(design.design):
         if self.port_type == 'rw':
             total_cin +=self.and2.get_cin() 
         return total_cin
+        
+    def graph_exclude_dffs(self):
+        """Exclude dffs from graph as they do not represent critical path"""
+        self.graph_inst_exclude.add(self.ctrl_dff_inst)

compiler/modules/dff.py

@@ -18,6 +18,7 @@ class dff(design.design):
     """
 
     pin_names = ["D", "Q", "clk", "vdd", "gnd"]
+    type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
     (width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"])
     
@@ -27,6 +28,7 @@ class dff(design.design):
         self.width = dff.width
         self.height = dff.height
         self.pin_map = dff.pin_map
+        self.add_pin_types(self.type_list)
     
     def analytical_power(self, corner, load):
         """Returns dynamic and leakage power. Results in nW"""
@@ -57,3 +59,7 @@ class dff(design.design):
         #Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width.
         return parameter["dff_clk_cin"]
 
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges based on inputs/outputs. Overrides base class function."""
+        self.add_graph_edges(graph, port_nets) 
+        

compiler/modules/hierarchical_decoder.py

@@ -624,3 +624,4 @@ class hierarchical_decoder(design.design):
         else:
             pre = self.pre3_8
         return pre.input_load()
+        

compiler/modules/precharge_array.py

@@ -115,3 +115,4 @@ class precharge_array(design.design):
         #Assume single port
         precharge_en_cin = self.pc_cell.get_en_cin()
         return precharge_en_cin*self.columns  
+        

compiler/modules/replica_bitline.py

@@ -25,6 +25,8 @@ class replica_bitline(design.design):
 
         self.bitcell_loads = bitcell_loads
         self.delay_fanout_list = delay_fanout_list
+        if len(delay_fanout_list) == 0 or len(delay_fanout_list)%2 == 1:
+            debug.error('Delay chain must contain an even amount of stages to maintain polarity.',1)
 
         self.create_netlist()
         if not OPTS.netlist_only:
@@ -86,7 +88,7 @@ class replica_bitline(design.design):
 
         self.replica_bitcell = factory.create(module_type="replica_bitcell")
         self.add_mod(self.replica_bitcell)
-
+        
         # This is the replica bitline load column that is the height of our array
         self.rbl = factory.create(module_type="bitcell_array",
                                   cols=1,

compiler/modules/sense_amp.py

@@ -20,6 +20,7 @@ class sense_amp(design.design):
     """
 
     pin_names = ["bl", "br", "dout", "en", "vdd", "gnd"]
+    type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
     (width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"])
 
@@ -30,7 +31,8 @@ class sense_amp(design.design):
         self.width = sense_amp.width
         self.height = sense_amp.height
         self.pin_map = sense_amp.pin_map
-
+        self.add_pin_types(self.type_list)
+        
     def input_load(self):
         #Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
         from tech import spice, parameter
@@ -58,4 +60,16 @@ class sense_amp(design.design):
         pmos_cin = parameter["sa_en_pmos_size"]/drc("minwidth_tx")
         nmos_cin = parameter["sa_en_nmos_size"]/drc("minwidth_tx")
         #sen is connected to 2 pmos isolation TX and 1 nmos per sense amp.
-        return 2*pmos_cin + nmos_cin
+        return 2*pmos_cin + nmos_cin
+    
+    def get_enable_name(self):
+        """Returns name used for enable net"""
+        #FIXME: A better programmatic solution to designate pins
+        enable_name = "en"
+        debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name))
+        return enable_name
+    
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges based on inputs/outputs. Overrides base class function."""
+        self.add_graph_edges(graph, port_nets) 
+        

compiler/modules/tri_gate.py

@@ -17,7 +17,8 @@ class tri_gate(design.design):
     netlist should be available in the technology library.  
     """
 
-    pin_names = ["in", "en", "en_bar", "out", "gnd", "vdd"]
+    pin_names = ["in", "out", "en", "en_bar", "vdd", "gnd"]
+    type_list = ["INPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
     (width,height) = utils.get_libcell_size("tri_gate", GDS["unit"], layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "tri_gate", GDS["unit"])
 
@@ -33,6 +34,7 @@ class tri_gate(design.design):
         self.width = tri_gate.width
         self.height = tri_gate.height
         self.pin_map = tri_gate.pin_map
+        self.add_pin_types(self.type_list)
 
     def analytical_delay(self, corner, slew, load=0.0):
         from tech import spice
@@ -49,3 +51,6 @@ class tri_gate(design.design):
     def input_load(self):
         return 9*spice["min_tx_gate_c"]
 
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges based on inputs/outputs. Overrides base class function."""
+        self.add_graph_edges(graph, port_nets) 

compiler/modules/write_driver.py

@@ -18,7 +18,8 @@ class write_driver(design.design):
     the technology library.
     """
 
-    pin_names = ["din", "bl", "br", "en", "gnd", "vdd"]
+    pin_names = ["din", "bl", "br", "en", "vdd", "gnd"]
+    type_list = ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
     (width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "write_driver", GDS["unit"])
 
@@ -29,9 +30,13 @@ class write_driver(design.design):
         self.width = write_driver.width
         self.height = write_driver.height
         self.pin_map = write_driver.pin_map
-
+        self.add_pin_types(self.type_list)
 
     def get_w_en_cin(self):
         """Get the relative capacitance of a single input"""
         # This is approximated from SCMOS. It has roughly 5 3x transistor gates.
         return 5*3
+
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges based on inputs/outputs. Overrides base class function."""
+        self.add_graph_edges(graph, port_nets)