mirror of https://github.com/VLSIDA/OpenRAM.git
Make wmask test a 1rw/1r
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parent
617a84d4b8
commit
239b3ea007
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@ -26,8 +26,8 @@ class sram_wmask_1w_1r_func_test(openram_test):
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OPTS.analytical_delay = False
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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OPTS.trim_netlist = False
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OPTS.num_rw_ports = 0
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 1
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OPTS.num_r_ports = 1
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globals.setup_bitcell()
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globals.setup_bitcell()
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