mirror of https://github.com/VLSIDA/OpenRAM.git
modules: Create a class that wraps all the module class names
this removes hard coded values from the module instatiations. It also allows users to override certain modules with their custom cells. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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class ModuleType():
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"""
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This is a class that maps cell names to python classes implementing them.
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"""
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def __init__(self):
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self.names = {}
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self.names['contact'] = 'contact'
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self.names['precharge'] = 'precharge'
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self.names['pinv'] = 'pinv'
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self.names['dff_buf'] = 'dff_buf'
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self.names['sense_amp'] = 'sense_amp'
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self.names['bitcell'] = 'bitcell'
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self.names['port_data'] = 'port_data'
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self.names['port_address'] = 'port_address'
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self.names['replica_bitcell_array'] = 'replica_bitcell_array'
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self.names['bank_select'] = 'bank_select'
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self.names['dff'] = 'dff'
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self.names['pinvbuf'] = 'pinvbuf'
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self.names['hierarchical_predecode2x4'] = 'hierarchical_predecode2x4'
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self.names['hierarchical_predecode3x8'] = 'hierarchical_predecode3x8'
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self.names['replica_bitcell'] = 'replica_bitcell'
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self.names['dummy_bitcell'] = 'dummy_bitcell'
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self.names['bitcell'] = 'bitcell'
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self.names['pnor2'] = 'pnor2'
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self.names['pnand2'] = 'pnand2'
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self.names['precharge_array'] = 'precharge_array'
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self.names['sense_amp_array'] = 'sense_amp_array'
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self.names['column_mux_array'] = 'column_mux_array'
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self.names['write_driver_array'] = 'write_driver_array'
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self.names['write_mask_and_array'] = 'write_mask_and_array'
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self.names['pand2'] = 'pand2'
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self.names['write_driver'] = 'write_driver'
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self.names['dff_buf_array'] = 'dff_buf_array'
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self.names['pdriver'] = 'pdriver'
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self.names['pand3'] = 'pand3'
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self.names['delay_chain'] = 'delay_chain'
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self.names['decoder'] = 'decoder'
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self.names['wordline_driver'] = 'wordline_driver'
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self.names['tri_gate'] = 'tri_gate'
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self.names['tri_gate_array'] = 'tri_gate_array'
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self.names['bitcell_array'] = 'bitcell_array'
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self.names['replica_column'] = 'replica_column'
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self.names['dummy_array'] = 'dummy_array'
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self.names['single_level_column_mux_array'] = 'single_level_column_mux_array'
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self.names['single_level_column_mux'] = 'single_level_column_mux'
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self.names['sram'] = 'sram'
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self.names['ptx'] = 'ptx'
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self.names['hierarchical_decoder'] = 'hierarchical_decoder'
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self.names['pbuf'] = 'pbuf'
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self.names['control_logic'] = 'control_logic'
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self.names['bank'] = 'bank'
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self.names['pbitcell'] = 'pbitcell'
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self.names['pnand3'] = 'pnand3'
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self.names['pwrite_driver'] = 'pwrite_driver'
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self.names['ptristate_inv'] = 'ptristate_inv'
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self.names['ptristate_buf'] = 'ptristate_buf'
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def __setitem__(self, b, c):
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self.names[b] = c
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def __getitem__(self, b):
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return self.names[b]
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