Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing.

compiler/tests/21_hspice_delay_test.py

@@ -50,7 +50,11 @@ class timing_sram_test(openram_test):
         import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
-        data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
+        data, port_data = d.analyze(probe_address, probe_data, load_slews)
         #Combine info about port into all data
         data.update(port_data[0])
 

compiler/tests/21_model_delay_test.py

@@ -55,13 +55,17 @@ class model_delay_test(openram_test):
         import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
 
         # Run a spice characterization
-        spice_data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        spice_data, port_data = d.analyze(probe_address, probe_data, load_slews)
         spice_data.update(port_data[0])
 
         # Run analytical characterization
-        model_data, port_data = m.get_lib_values(slews, loads)
+        model_data, port_data = m.get_lib_values(load_slews)
         model_data.update(port_data[0])
 
         # Only compare the delays
@@ -79,6 +83,9 @@ class model_delay_test(openram_test):
         else:
             self.assertTrue(False) # other techs fail
 
+        print('spice_delays', spice_delays)
+        print('model_delays', model_delays)
+
         # Check if no too many or too few results
         self.assertTrue(len(spice_delays.keys())==len(model_delays.keys()))
 

compiler/tests/21_ngspice_delay_extra_rows_test.py

@@ -51,7 +51,11 @@ class timing_sram_test(openram_test):
         import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
-        data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
+        data, port_data = d.analyze(probe_address, probe_data, load_slews)
         #Combine info about port into all data
         data.update(port_data[0])
 

compiler/tests/21_ngspice_delay_global_test.py

@@ -58,7 +58,11 @@ class timing_sram_test(openram_test):
         import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
-        data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
+        data, port_data = d.analyze(probe_address, probe_data, load_slews)
         #Combine info about port into all data
         data.update(port_data[0])
 

compiler/tests/21_ngspice_delay_test.py

@@ -50,7 +50,11 @@ class timing_sram_test(openram_test):
         import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
-        data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
+        data, port_data = d.analyze(probe_address, probe_data, load_slews)
         #Combine info about port into all data
         data.update(port_data[0])