Merge branch 'multiport_cleanup' of https://github.com/VLSIDA/PrivateRAM into multiport_cleanup

This commit is contained in:
Matt Guthaus
2018-07-11 14:27:06 -07:00
15 changed files with 138 additions and 46 deletions
+4 -4
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@@ -13,10 +13,8 @@ class library_drc_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc=True
(gds_dir, gds_files) = setup_files()
drc_errors = 0
debug.info(1, "\nPerforming DRC on: " + ", ".join(gds_files))
@@ -32,11 +30,12 @@ class library_drc_test(openram_test):
self.assertEqual(drc_errors, 0)
globals.end_openram()
def setup_files():
gds_dir = OPTS.openram_tech + "/gds_lib"
files = os.listdir(gds_dir)
nametest = re.compile("\.gds$", re.IGNORECASE)
gds_files = filter(nametest.search, files)
gds_files = list(filter(nametest.search, files))
return (gds_dir, gds_files)
@@ -46,3 +45,4 @@ if __name__ == "__main__":
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
+1 -1
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@@ -14,7 +14,7 @@ class library_lvs_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import verify
OPTS.check_lvsdrc=True
(gds_dir, sp_dir, allnames) = setup_files()
lvs_errors = 0
debug.info(1, "Performing LVS on: " + ", ".join(allnames))
+1 -1
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@@ -17,6 +17,7 @@ class timing_sram_test(openram_test):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name="hspice"
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
@@ -83,7 +84,6 @@ class timing_sram_test(openram_test):
else:
self.isclose(data[k],golden_data[k],0.15)
reload(characterizer)
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
@@ -26,7 +26,6 @@ class timing_setup_test(openram_test):
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
import sram
import tech
slews = [tech.spice["rise_time"]*2]
@@ -58,7 +57,6 @@ class timing_setup_test(openram_test):
else:
self.isclose(data[k],golden_data[k],0.15)
reload(characterizer)
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
-1
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@@ -83,7 +83,6 @@ class timing_sram_test(openram_test):
else:
self.isclose(data[k],golden_data[k],0.15)
reload(characterizer)
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
+11 -2
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@@ -16,6 +16,17 @@ class sram_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.use_pex = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import setup_hold
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
global verify
import verify
@@ -31,8 +42,6 @@ class sram_func_test(openram_test):
import tech
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
global OPTS
OPTS.use_pex = True
s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
-3
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@@ -73,10 +73,7 @@ class openram_test(openram_test):
shutil.rmtree(out_path, ignore_errors=True)
self.assertEqual(os.path.exists(out_path),False)
# The default was on, so disable it.
OPTS.check_lvsdrc=False
globals.end_openram()
OPTS.check_lvsdrc=True
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":
+9 -2
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@@ -28,5 +28,12 @@ suite = unittest.TestSuite()
load = unittest.defaultTestLoader.loadTestsFromModule
suite.addTests(map(load, modules))
ret = not unittest.TextTestRunner(verbosity=2).run(suite).wasSuccessful()
sys.exit(ret)
test_runner = unittest.TextTestRunner(verbosity=2,stream=sys.stderr)
test_result = test_runner.run(suite)
import verify
verify.print_drc_stats()
verify.print_lvs_stats()
verify.print_pex_stats()
sys.exit(not test_result.wasSuccessful())