mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 09:30:38 +02:00
Merge branch 'multiport_cleanup' of https://github.com/VLSIDA/PrivateRAM into multiport_cleanup
This commit is contained in:
@@ -13,10 +13,8 @@ class library_drc_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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global verify
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import verify
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OPTS.check_lvsdrc=True
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(gds_dir, gds_files) = setup_files()
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drc_errors = 0
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debug.info(1, "\nPerforming DRC on: " + ", ".join(gds_files))
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@@ -32,11 +30,12 @@ class library_drc_test(openram_test):
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self.assertEqual(drc_errors, 0)
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globals.end_openram()
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def setup_files():
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gds_dir = OPTS.openram_tech + "/gds_lib"
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files = os.listdir(gds_dir)
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nametest = re.compile("\.gds$", re.IGNORECASE)
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gds_files = filter(nametest.search, files)
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gds_files = list(filter(nametest.search, files))
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return (gds_dir, gds_files)
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@@ -46,3 +45,4 @@ if __name__ == "__main__":
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@@ -14,7 +14,7 @@ class library_lvs_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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import verify
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OPTS.check_lvsdrc=True
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(gds_dir, sp_dir, allnames) = setup_files()
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lvs_errors = 0
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debug.info(1, "Performing LVS on: " + ", ".join(allnames))
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@@ -17,6 +17,7 @@ class timing_sram_test(openram_test):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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@@ -83,7 +84,6 @@ class timing_sram_test(openram_test):
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else:
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self.isclose(data[k],golden_data[k],0.15)
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reload(characterizer)
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globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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@@ -26,7 +26,6 @@ class timing_setup_test(openram_test):
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if not OPTS.spice_exe:
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debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
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import sram
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import tech
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slews = [tech.spice["rise_time"]*2]
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@@ -58,7 +57,6 @@ class timing_setup_test(openram_test):
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else:
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self.isclose(data[k],golden_data[k],0.15)
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reload(characterizer)
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globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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@@ -83,7 +83,6 @@ class timing_sram_test(openram_test):
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else:
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self.isclose(data[k],golden_data[k],0.15)
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reload(characterizer)
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globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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@@ -16,6 +16,17 @@ class sram_func_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.use_pex = True
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import setup_hold
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if not OPTS.spice_exe:
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debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
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global verify
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import verify
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@@ -31,8 +42,6 @@ class sram_func_test(openram_test):
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import tech
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debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
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global OPTS
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OPTS.use_pex = True
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s = sram.sram(word_size=OPTS.word_size,
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num_words=OPTS.num_words,
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num_banks=OPTS.num_banks,
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@@ -73,10 +73,7 @@ class openram_test(openram_test):
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shutil.rmtree(out_path, ignore_errors=True)
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self.assertEqual(os.path.exists(out_path),False)
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# The default was on, so disable it.
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OPTS.check_lvsdrc=False
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globals.end_openram()
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OPTS.check_lvsdrc=True
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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@@ -28,5 +28,12 @@ suite = unittest.TestSuite()
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load = unittest.defaultTestLoader.loadTestsFromModule
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suite.addTests(map(load, modules))
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ret = not unittest.TextTestRunner(verbosity=2).run(suite).wasSuccessful()
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sys.exit(ret)
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test_runner = unittest.TextTestRunner(verbosity=2,stream=sys.stderr)
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test_result = test_runner.run(suite)
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import verify
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verify.print_drc_stats()
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verify.print_lvs_stats()
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verify.print_pex_stats()
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sys.exit(not test_result.wasSuccessful())
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