Begin wmask functionality. Added wmask to verilog file and config parameters.

compiler/globals.py

@@ -20,8 +20,8 @@ import copy
 import importlib
 
 USAGE = "Usage: openram.py [options] <config file>\nUse -h for help.\n"
-
 # Anonymous object that will be the options
+
 OPTS = options.options()
 CHECKPOINT_OPTS=None
 
@@ -464,6 +464,18 @@ def report_status():
         debug.error("{0} is not an integer in config file.".format(OPTS.word_size))
     if type(OPTS.num_words)!=int:
         debug.error("{0} is not an integer in config file.".format(OPTS.sram_size))
+    if type(OPTS.write_size) != int and OPTS.write_size != None:
+        debug.error("{0} is not an integer in config file.".format(OPTS.write_size))
+
+    # Determine if a write mask is specified by the user; if it's not, the mask write size should
+    # be the same as the word size so that an entire word is written at once
+    if OPTS.write_size==None:
+        OPTS.write_size = OPTS.word_size
+
+    if  (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size):
+        debug.error("Write size needs to be between 1 bit and {0} bits.".format(OPTS.word_size))
+    if (OPTS.word_size % OPTS.write_size != 0):
+        debug.error("Write size needs to be an integer multiple of word size.")
 
     if not OPTS.tech_name:
         debug.error("Tech name must be specified in config file.")
@@ -477,9 +489,12 @@ def report_status():
     debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
                                                           OPTS.num_words,
                                                           OPTS.num_banks))
+    if (OPTS.write_size != OPTS.word_size):
+        debug.print_raw("Write size: {}".format(OPTS.write_size))
     debug.print_raw("RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format(OPTS.num_rw_ports,
                                                                        OPTS.num_r_ports,
                                                                        OPTS.num_w_ports))
+
     if OPTS.netlist_only:
         debug.print_raw("Netlist only mode (no physical design is being done, netlist_only=False to disable).")
     

compiler/modules/bank.py

@@ -79,6 +79,9 @@ class bank(design.design):
         for port in self.write_ports:
             for bit in range(self.word_size):
                 self.add_pin("din{0}_{1}".format(port,bit),"IN")
+        # if (self.word_size != self.write_size):
+        #     for bit in range(self.word_size):
+        #         self.add_pin()
         for port in self.all_ports:
             for bit in range(self.addr_size):
                 self.add_pin("addr{0}_{1}".format(port,bit),"INPUT")

compiler/openram.py

@@ -50,7 +50,8 @@ from sram_config import sram_config
 
 # Configure the SRAM organization
 c = sram_config(word_size=OPTS.word_size,
-                num_words=OPTS.num_words)
+                num_words=OPTS.num_words,
+                write_size=OPTS.write_size)
 debug.print_raw("Words per row: {}".format(c.words_per_row))
 
 #from parser import *

compiler/options.py

@@ -8,6 +8,7 @@
 import optparse
 import getpass 
 import os
+#import sram_config
 
 class options(optparse.Values):
     """
@@ -28,6 +29,9 @@ class options(optparse.Values):
     num_rw_ports = 1
     num_r_ports = 0
     num_w_ports = 0
+
+    # Write mask size, default will be overwritten with word_size if not user specified
+    write_size = None
     
     # These will get initialized by the user or the tech file
     supply_voltages = ""

compiler/sram/sram_base.py

@@ -68,7 +68,10 @@ class sram_base(design, verilog, lef):
             self.add_pin("web{}".format(port),"INPUT")
         for port in self.all_ports:
             self.add_pin("clk{}".format(port),"INPUT")
-
+        # add the optional write mask pins
+        if self.word_size != self.write_size:
+            for port in self.write_ports:
+                self.add_pin("wmask{}".format(port),"INPUT")
         for port in self.read_ports:
             for bit in range(self.word_size):
                 self.add_pin("DOUT{0}[{1}]".format(port,bit),"OUTPUT")
@@ -150,9 +153,6 @@ class sram_base(design, verilog, lef):
         rtr.route()
 
         
-
-        
-        
     def compute_bus_sizes(self):
         """ Compute the independent bus widths shared between two and four bank SRAMs """
         
@@ -464,8 +464,22 @@ class sram_base(design, verilog, lef):
             if port in self.readwrite_ports:
                 temp.append("web{}".format(port))
             temp.append("clk{}".format(port))
+            # if port in self.write_ports:
+            #     temp.append("wmask{}".format(port))
 
-            # Ouputs
+            # for port in self.all_ports:
+            #     self.add_pin("csb{}".format(port), "INPUT")
+            # for port in self.readwrite_ports:
+            #     self.add_pin("web{}".format(port), "INPUT")
+            # for port in self.all_ports:
+            #     self.add_pin("clk{}".format(port), "INPUT")
+            # # add the optional write mask pins
+            # if self.word_size != self.write_size:
+            #     for port in self.write_ports:
+            #         print("write_ports", port)
+            #         self.add_pin("wmask{0}".format(port), "INPUT")
+
+            # Outputs
             if port in self.read_ports:
                 temp.append("s_en{}".format(port))
             if port in self.write_ports:

compiler/sram/sram_config.py

@@ -14,16 +14,20 @@ from sram_factory import factory
 class sram_config:
     """ This is a structure that is used to hold the SRAM configuration options. """
     
-    def __init__(self, word_size, num_words, num_banks=1, words_per_row=None):
+    def __init__(self, word_size, num_words, write_size = None, num_banks=1, words_per_row=None):
         self.word_size = word_size
         self.num_words = num_words
+        self.write_size = write_size
         self.num_banks = num_banks
 
         # This will get over-written when we determine the organization
         self.words_per_row = words_per_row
 
+        if OPTS.write_size == None:
+            OPTS.write_size = OPTS.word_size
+
         self.compute_sizes()
-        
+
 
     def set_local_config(self, module):
         """ Copy all of the member variables to the given module for convenience """