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Begin wmask functionality. Added wmask to verilog file and config parameters.
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@@ -79,6 +79,9 @@ class bank(design.design):
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for port in self.write_ports:
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for bit in range(self.word_size):
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self.add_pin("din{0}_{1}".format(port,bit),"IN")
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# if (self.word_size != self.write_size):
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# for bit in range(self.word_size):
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# self.add_pin()
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for port in self.all_ports:
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for bit in range(self.addr_size):
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self.add_pin("addr{0}_{1}".format(port,bit),"INPUT")
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