mirror of https://github.com/VLSIDA/OpenRAM.git
Fix ms_flop array for M3 supplies
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@ -71,14 +71,16 @@ class ms_flop_array(design.design):
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for i in range(self.word_size):
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for gnd_pin in self.ms_inst[i].get_pins("gnd"):
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if gnd_pin.layer!="metal2":
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continue
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self.add_layout_pin(text="gnd",
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layer="metal2",
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offset=gnd_pin.ll(),
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width=gnd_pin.width(),
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height=gnd_pin.height())
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# Route both supplies
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for n in ["vdd", "gnd"]:
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for supply_pin in self.ms_inst[i].get_pins(n):
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pin_pos = supply_pin.center()
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=pin_pos)
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self.add_layout_pin_rect_center(text=n,
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layer="metal3",
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offset=pin_pos)
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din_pins = self.ms_inst[i].get_pins("din")
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for din_pin in din_pins:
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@ -110,26 +112,9 @@ class ms_flop_array(design.design):
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width=self.width,
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height=drc["minwidth_metal1"])
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# Continous vdd rail along with label.
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for vdd_pin in self.ms_inst[i].get_pins("vdd"):
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if vdd_pin.layer!="metal1":
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continue
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll().scale(0,1),
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width=self.width,
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height=drc["minwidth_metal1"])
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# Continous gnd rail along with label.
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for gnd_pin in self.ms_inst[i].get_pins("gnd"):
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if gnd_pin.layer!="metal1":
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continue
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll().scale(0,1),
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width=self.width,
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height=drc["minwidth_metal1"])
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def analytical_delay(self, slew, load=0.0):
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