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Merge branch 'dev' into cacti_model

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Hunter Nichols
2021-07-26 14:35:47 -07:00
parent 3e0a49e58d cce1305da3
commit 1e08005639
29 changed files with 873 additions and 112 deletions
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compiler/modules/bank.py
+1 -1
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@@ -620,7 +620,7 @@ class bank(design.design):
self.copy_power_pins(inst, "gnd", add_vias=False)
if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
for pin_name, supply_name in zip(['vpb','vnb'],['gnd','vdd']):
for pin_name, supply_name in zip(['vnb','vpb'],['gnd','vdd']):
self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name)
# If we use the pinvbuf as the decoder, we need to add power pins.
compiler/modules/bitcell_base_array.py
-3
View File
@@ -162,9 +162,6 @@ class bitcell_base_array(design.design):
inst = self.cell_inst[row, col]
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)
if row == 2: #add only 1 label per col
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)
def add_layout_pins(self):
""" Add the layout pins """