mirror of https://github.com/VLSIDA/OpenRAM.git
Add func random seed as input option and log out
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@ -7,6 +7,7 @@
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#
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#
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import math
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import math
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import random
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import random
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import time
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import collections
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import collections
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from os import path
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from os import path
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import shutil
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import shutil
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@ -31,6 +32,13 @@ class functional(simulation):
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# Seed the characterizer with a constant seed for unit tests
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# Seed the characterizer with a constant seed for unit tests
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if OPTS.is_unit_test:
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if OPTS.is_unit_test:
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random.seed(12345)
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random.seed(12345)
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elif OPTS.functional_seed:
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random.seed(OPTS.functional_seed)
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else:
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seed = time.time_ns()
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random.seed(seed)
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debug.info(1, "Random seed for functional simulation: {}".format(seed))
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if not spfile:
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if not spfile:
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# self.sp_file is assigned in base class
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# self.sp_file is assigned in base class
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@ -185,6 +185,10 @@ class options(optparse.Values):
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br_format = "X{name}{hier_sep}xbank0{hier_sep}br_{row}_{col}"
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br_format = "X{name}{hier_sep}xbank0{hier_sep}br_{row}_{col}"
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sen_format = "X{name}{hier_sep}xbank0{hier_sep}s_en"
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sen_format = "X{name}{hier_sep}xbank0{hier_sep}s_en"
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cell_format = "X{name}{hier_sep}xbank0{hier_sep}xbitcell_array{hier_sep}xreplica_bitcell_array{hier_sep}xbitcell_array{hier_sep}xbit_r{row}_c{col}"
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cell_format = "X{name}{hier_sep}xbank0{hier_sep}xbitcell_array{hier_sep}xreplica_bitcell_array{hier_sep}xbitcell_array{hier_sep}xbit_r{row}_c{col}"
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# Random seed for functional simulation
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functional_seed = None
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# Route the input/output pins to the perimeter
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# Route the input/output pins to the perimeter
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perimeter_pins = True
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perimeter_pins = True
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