mirror of https://github.com/VLSIDA/OpenRAM.git
fixed issue with read ports that caused extra transistors to appear
This commit is contained in:
Michael Timothy Grimes
parent
e804f36bec
commit
1d5a41df2d
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@ -36,8 +36,6 @@ class pbitcell(pgate.pgate):
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pbitcell.width = self.width
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pbitcell.height = self.height
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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@ -90,7 +88,6 @@ class pbitcell(pgate.pgate):
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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# if there are any read/write ports, then the inverter nmos is sized based the number of them
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if(self.num_readwrite > 0):
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@ -133,7 +130,6 @@ class pbitcell(pgate.pgate):
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tx_type="nmos")
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self.add_mod(self.read_nmos)
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def calculate_spacing(self):
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""" Calculate transistor spacings """
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@ -268,6 +264,31 @@ class pbitcell(pgate.pgate):
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self.height = self.topmost_ypos - self.botmost_ypos - array_vdd_overlap
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def create_storage(self):
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"""
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Creates the crossed coupled inverters that act as storage for the bitcell.
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The stored value of the cell is denoted as "Q", and the inverted value as "Q_bar".
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"""
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# create active for nmos
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self.inverter_nmos_left = self.add_inst(name="inverter_nmos_left",
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mod=self.inverter_nmos)
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self.connect_inst(["Q_bar", "Q", "gnd", "gnd"])
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self.inverter_nmos_right = self.add_inst(name="inverter_nmos_right",
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mod=self.inverter_nmos)
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self.connect_inst(["gnd", "Q_bar", "Q", "gnd"])
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# create active for pmos
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self.inverter_pmos_left = self.add_inst(name="inverter_pmos_left",
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mod=self.inverter_pmos)
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self.connect_inst(["Q_bar", "Q", "vdd", "vdd"])
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self.inverter_pmos_right = self.add_inst(name="inverter_pmos_right",
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mod=self.inverter_pmos)
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self.connect_inst(["vdd", "Q_bar", "Q", "vdd"])
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def place_storage(self):
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"""
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Places the crossed coupled inverters that act as storage for the bitcell.
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@ -320,31 +341,6 @@ class pbitcell(pgate.pgate):
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self.right_building_edge = self.inverter_tile_width
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def create_storage(self):
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"""
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Creates the crossed coupled inverters that act as storage for the bitcell.
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The stored value of the cell is denoted as "Q", and the inverted value as "Q_bar".
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"""
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# create active for nmos
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self.inverter_nmos_left = self.add_inst(name="inverter_nmos_left",
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mod=self.inverter_nmos)
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self.connect_inst(["Q_bar", "Q", "gnd", "gnd"])
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self.inverter_nmos_right = self.add_inst(name="inverter_nmos_right",
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mod=self.inverter_nmos)
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self.connect_inst(["gnd", "Q_bar", "Q", "gnd"])
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# create active for pmos
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self.inverter_pmos_left = self.add_inst(name="inverter_pmos_left",
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mod=self.inverter_pmos)
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self.connect_inst(["Q_bar", "Q", "vdd", "vdd"])
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self.inverter_pmos_right = self.add_inst(name="inverter_pmos_right",
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mod=self.inverter_pmos)
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self.connect_inst(["vdd", "Q_bar", "Q", "vdd"])
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def route_rails(self):
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"""
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Add gnd and vdd rails and connects them to the inverters
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@ -816,15 +812,6 @@ class pbitcell(pgate.pgate):
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# calculate offset to overlap the drain of the read-access transistor with the source of the read transistor
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overlap_offset = self.read_nmos.get_pin("D").ll() - self.read_nmos.get_pin("S").ll()
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# define read transistor variables as empty arrays based on the number of read ports
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self.read_nmos_left = [None] * self.num_read
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self.read_nmos_right = [None] * self.num_read
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self.read_access_nmos_left = [None] * self.num_read
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self.read_access_nmos_right = [None] * self.num_read
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self.rwl_positions = [None] * self.num_read
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self.rbl_positions = [None] * self.num_read
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self.rbl_bar_positions = [None] * self.num_read
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# iterate over the number of read ports
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for k in range(0,self.num_read):
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# Add transistors
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@ -840,30 +827,18 @@ class pbitcell(pgate.pgate):
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+ read_rotation_correct
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# add read-access transistors
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self.read_access_nmos_left[k] = self.add_inst(name="read_access_nmos_left{}".format(k),
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mod=self.read_nmos,
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offset=[left_read_transistor_xpos,0],
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self.read_access_nmos_left[k].place(offset=[left_read_transistor_xpos,0],
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rotate=90)
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self.connect_inst(["RA_to_R_left{}".format(k), " Q_bar", "gnd", "gnd"])
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self.read_access_nmos_right[k] = self.add_inst(name="read_access_nmos_right{}".format(k),
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mod=self.read_nmos,
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offset=[right_read_transistor_xpos,0],
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self.read_access_nmos_right[k].place(offset=[right_read_transistor_xpos,0],
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rotate=90)
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self.connect_inst(["RA_to_R_right{}".format(k), "Q", "gnd", "gnd"])
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# add read transistors
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self.read_nmos_left[k] = self.add_inst(name="read_nmos_left{}".format(k),
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mod=self.read_nmos,
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offset=[left_read_transistor_xpos,overlap_offset.x],
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self.read_nmos_left[k].place(offset=[left_read_transistor_xpos,overlap_offset.x],
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rotate=90)
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self.connect_inst(["rbl{}".format(k), "rwl{}".format(k), "RA_to_R_left{}".format(k), "gnd"])
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self.read_nmos_right[k] = self.add_inst(name="read_nmos_right{}".format(k),
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mod=self.read_nmos,
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offset=[right_read_transistor_xpos,overlap_offset.x],
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self.read_nmos_right[k].place(offset=[right_read_transistor_xpos,overlap_offset.x],
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rotate=90)
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self.connect_inst(["rbl_bar{}".format(k), "rwl{}".format(k), "RA_to_R_right{}".format(k), "gnd"])
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# Add RWL lines
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# calculate RWL position
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