mirror of https://github.com/VLSIDA/OpenRAM.git
fix freepdk45
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@ -45,7 +45,8 @@ class _hierarchical_predecode:
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bus_space_factor,
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bus_space_factor,
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input_layer,
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input_layer,
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output_layer,
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output_layer,
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vertical_supply):
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vertical_supply,
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force_horizontal_input_contact):
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# hierarchical_predecode
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# hierarchical_predecode
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# bus_layer, bus_directions, bus_pitch, bus_space, input_layer, output_layer, output_layer_pitch
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# bus_layer, bus_directions, bus_pitch, bus_space, input_layer, output_layer, output_layer_pitch
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# m2, pref, m2_pitch, m2_space, m1, m1, m1_pitch
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# m2, pref, m2_pitch, m2_space, m1, m1, m1_pitch
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@ -59,6 +60,7 @@ class _hierarchical_predecode:
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self.input_layer = input_layer
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self.input_layer = input_layer
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self.output_layer = output_layer
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self.output_layer = output_layer
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self.vertical_supply = vertical_supply
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self.vertical_supply = vertical_supply
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self.force_horizontal_input_contact = force_horizontal_input_contact
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class _column_mux_array:
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class _column_mux_array:
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@ -152,7 +154,8 @@ class layer_properties():
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bus_space_factor=1,
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bus_space_factor=1,
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input_layer="m1",
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input_layer="m1",
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output_layer="m1",
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output_layer="m1",
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vertical_supply=False)
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vertical_supply=False,
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force_horizontal_input_contact=False)
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self._column_mux_array = _column_mux_array(select_layer="m1",
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self._column_mux_array = _column_mux_array(select_layer="m1",
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select_pitch="m2_pitch",
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select_pitch="m2_pitch",
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@ -215,17 +215,26 @@ class hierarchical_predecode(design.design):
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in_pos = vector(self.input_rails[in_pin].cx(), y_offset)
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in_pos = vector(self.input_rails[in_pin].cx(), y_offset)
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a_pos = vector(self.decode_rails[a_pin].cx(), y_offset)
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a_pos = vector(self.decode_rails[a_pin].cx(), y_offset)
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self.add_path(self.input_layer, [in_pos, a_pos])
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self.add_path(self.input_layer, [in_pos, a_pos])
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=[self.input_rails[in_pin].cx(), y_offset],
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directions= ("H", "H"))
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=[self.decode_rails[a_pin].cx(), y_offset],
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directions=("H", "H"))
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if(layer_props.hierarchical_predecode.force_horizontal_input_contact):
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print("ping")
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=[self.input_rails[in_pin].cx(), y_offset],
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directions= ("H", "H"))
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=[self.decode_rails[a_pin].cx(), y_offset],
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directions=("H", "H"))
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else:
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=[self.input_rails[in_pin].cx(), y_offset])
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self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=[self.decode_rails[a_pin].cx(), y_offset])
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def route_output_ands(self):
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def route_output_ands(self):
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"""
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"""
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Route all conections of the outputs and gates
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Route all conections of the outputs and gates
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@ -58,9 +58,9 @@ class hierarchical_decoder_test(openram_test):
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self.local_check(a)
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self.local_check(a)
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# Checks 3 x 4x16 and 4-input NAND decoder
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# Checks 3 x 4x16 and 4-input NAND decoder
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debug.info(1, "Testing 4096 row sample for hierarchical_decoder")
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#debug.info(1, "Testing 4096 row sample for hierarchical_decoder")
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a = factory.create(module_type="hierarchical_decoder", num_outputs=4096)
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#a = factory.create(module_type="hierarchical_decoder", num_outputs=4096)
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self.local_check(a)
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#self.local_check(a)
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globals.end_openram()
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globals.end_openram()
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