luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

fix freepdk45

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2021-06-17 03:21:01 -07:00
parent 1e486cd344
commit 1ce6b4d41a
3 changed files with 27 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/hierarchical_predecode.py
+19 -10
View File
@@ -215,17 +215,26 @@ class hierarchical_predecode(design.design):
in_pos = vector(self.input_rails[in_pin].cx(), y_offset)
a_pos = vector(self.decode_rails[a_pin].cx(), y_offset)
self.add_path(self.input_layer, [in_pos, a_pos])
self.add_via_stack_center(from_layer=self.input_layer,
to_layer=self.bus_layer,
offset=[self.input_rails[in_pin].cx(), y_offset],
directions= ("H", "H"))
self.add_via_stack_center(from_layer=self.input_layer,
to_layer=self.bus_layer,
offset=[self.decode_rails[a_pin].cx(), y_offset],
directions=("H", "H"))
if(layer_props.hierarchical_predecode.force_horizontal_input_contact):
print("ping")
self.add_via_stack_center(from_layer=self.input_layer,
to_layer=self.bus_layer,
offset=[self.input_rails[in_pin].cx(), y_offset],
directions= ("H", "H"))
self.add_via_stack_center(from_layer=self.input_layer,
to_layer=self.bus_layer,
offset=[self.decode_rails[a_pin].cx(), y_offset],
directions=("H", "H"))
else:
self.add_via_stack_center(from_layer=self.input_layer,
to_layer=self.bus_layer,
offset=[self.input_rails[in_pin].cx(), y_offset])
self.add_via_stack_center(from_layer=self.input_layer,
to_layer=self.bus_layer,
offset=[self.decode_rails[a_pin].cx(), y_offset])
def route_output_ands(self):
"""
Route all conections of the outputs and gates