Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

compiler/modules/bank.py

@@ -392,14 +392,12 @@ class bank(design.design):
                                                 cols=self.num_cols + self.num_spare_cols,
                                                 rows=self.num_rows)
         self.add_mod(self.bitcell_array)
-        if self.num_spare_cols == 0:
-            self.num_spare_cols = (self.bitcell_array.column_size % (self.word_size *self.words_per_row))
 
         self.port_address = []
         for port in self.all_ports:
             self.port_address.append(factory.create(module_type="port_address",
-                                                    cols=self.bitcell_array.column_size,
+                                                    cols=self.num_cols + self.num_spare_cols,
-                                                    rows=self.bitcell_array.row_size,
+                                                    rows=self.num_rows,
                                                     port=port))
             self.add_mod(self.port_address[port])
 
@@ -408,10 +406,6 @@ class bank(design.design):
         for port in self.all_ports:
             temp_pre = factory.create(module_type="port_data",
                                       sram_config=self.sram_config,
-                                      dimension_override=True,
-                                      cols=self.bitcell_array.column_size - self.num_spare_cols,
-                                      rows=self.bitcell_array.row_size,
-                                      num_spare_cols=self.num_spare_cols,
                                       port=port,
                                       bit_offsets=self.bit_offsets)
             self.port_data.append(temp_pre)
@@ -500,7 +494,7 @@ class bank(design.design):
                                                          mod=self.port_address[port])
 
             temp = []
-            for bit in range(ceil(log(self.bitcell_array.row_size, 2))):
+            for bit in range(self.row_addr_size):
                 temp.append("addr{0}_{1}".format(port, bit + self.col_addr_size))
             temp.append("wl_en{}".format(port))
             wordline_names = self.bitcell_array.get_wordline_names(port)

compiler/modules/port_data.py

@@ -21,24 +21,19 @@ class port_data(design.design):
     Port 0 always has the RBL on the left while port 1 is on the right.
     """
 
-    def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="", rows=None, cols=None, dimension_override=False):
+    def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="",):
-        sram_config.set_local_config(self)
-        if dimension_override:
-            self.num_rows = rows
-            self.num_cols = cols
-            self.word_size = sram_config.word_size
 
+        sram_config.set_local_config(self)
         self.port = port
         if self.write_size is not None:
             self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
         else:
             self.num_wmasks = 0
         
-        if num_spare_cols:
+        if num_spare_cols is not None:
-            self.num_spare_cols = num_spare_cols
+                self.num_spare_cols = num_spare_cols + self.num_spare_cols
-        elif self.num_spare_cols is None:
+        if self.num_spare_cols is None:
             self.num_spare_cols = 0
-
         if not bit_offsets:
             bitcell = factory.create(module_type=OPTS.bitcell)
             if(cell_properties.use_strap == True and OPTS.num_ports == 1):

compiler/sram/sram_config.py

@@ -9,6 +9,8 @@ import debug
 from math import log, sqrt, ceil
 from globals import OPTS
 from sram_factory import factory
+from tech import array_row_multiple
+from tech import array_col_multiple
 
 
 class sram_config:
@@ -96,6 +98,15 @@ class sram_config:
                    + " Col addr size: {}".format(self.col_addr_size)
                    + " Bank addr size: {}".format(self.bank_addr_size))
 
+        num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
+        print(num_ports)
+        if num_ports == 1:
+            if ((self.num_cols + num_ports + self.num_spare_cols) % array_col_multiple != 0):
+                debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, array_col_multiple), -1)
+
+            if ((self.num_rows + num_ports) % array_row_multiple != 0):
+                debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.num_rows + num_ports, array_row_multiple), -1)
+                
     def estimate_words_per_row(self, tentative_num_cols, word_size):
         """
         This provides a heuristic rounded estimate for the number of words

technology/freepdk45/tech/tech.py

@@ -465,3 +465,6 @@ lvs_name = "calibre"
 pex_name = "calibre"
 
 blackbox_bitcell = False
+
+array_row_multiple = 1
+array_col_multiple = 1

technology/scn3me_subm/tech/tech.py

@@ -305,3 +305,5 @@ pex_name = "magic"
 ###################################################
 ##END Technology Tool Preferences
 ###################################################
+array_row_multiple = 1
+array_col_multiple = 1

technology/scn4m_subm/tech/tech.py

@@ -412,3 +412,6 @@ lvs_name = "netgen"
 pex_name = "magic"
 
 blackbox_bitcell = False
+
+array_row_multiple = 1
+array_col_multiple = 1