Merge branch 'sky130_fixes' into dev

Makefile

@@ -10,19 +10,19 @@ PDK_ROOT ?= $(TOP_DIR)
 SRAM_LIB_DIR ?= $(PDK_ROOT)/sky130_fd_bd_sram
 SRAM_LIB_GIT_REPO ?= https://github.com/vlsida/sky130_fd_bd_sram.git
 #SRAM_LIB_GIT_REPO ?= https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git
-SRAM_LIB_GIT_COMMIT ?= main
+SRAM_LIB_GIT_COMMIT ?= 95287ef89556505b2cdf17912c025cb74d9288a7
 
 # Open PDKs
 OPEN_PDKS_DIR ?= $(PDK_ROOT)/open_pdks
 OPEN_PDKS_GIT_REPO ?= https://github.com/RTimothyEdwards/open_pdks.git
 #OPEN_PDKS_GIT_COMMIT ?= 1.0.156
-OPEN_PDKS_GIT_COMMIT ?= master
+OPEN_PDKS_GIT_COMMIT ?= 7ea416610339d3c29af9d0d748ceadd3fd368608
 SKY130_PDK ?= $(PDK_ROOT)/sky130A
 
 # Skywater PDK
 SKY130_PDKS_DIR ?= $(PDK_ROOT)/skywater-pdk
 SKY130_PDKS_GIT_REPO ?= https://github.com/google/skywater-pdk.git
-SKY130_PDKS_GIT_COMMIT ?= main
+SKY130_PDKS_GIT_COMMIT ?= f70d8ca46961ff92719d8870a18a076370b85f6c
 
 # Create lists of all the files to copy/link
 GDS_FILES := $(sort $(wildcard $(SRAM_LIB_DIR)/cells/*/*.gds))

compiler/modules/dff_buf_array.py

@@ -154,7 +154,7 @@ class dff_buf_array(design.design):
             gndn_pin=self.dff_insts[row, self.columns - 1].get_pin("gnd")
             self.add_path(gnd0_pin.layer, [gnd0_pin.lc(), gndn_pin.rc()], width=gnd0_pin.height())
 
-        if OPTS.experimental_power and self.rows > 1:
+        if self.rows > 1:
             # Vertical straps on ends if multiple rows
             left_dff_insts = [self.dff_insts[x, 0] for x in range(self.rows)]
             right_dff_insts = [self.dff_insts[x, self.columns-1] for x in range(self.rows)]

compiler/modules/write_driver_array.py

@@ -256,15 +256,7 @@ class write_driver_array(design.design):
                                 width=self.width)
 
     def route_supplies(self):
-        if OPTS.experimental_power:
+        self.route_horizontal_pins("vdd")
-            self.route_horizontal_pins("vdd")
+        self.route_horizontal_pins("gnd")
-            self.route_horizontal_pins("gnd")
-        else:
-            for i in range(self.word_size + self.num_spare_cols):
-                inst = self.local_insts[i]
-                for n in ["vdd", "gnd"]:
-                    pin_list = inst.get_pins(n)
-                    for pin in pin_list:
-                        self.copy_power_pin(pin, directions=("V", "V"))
 
 

compiler/options.py

@@ -194,6 +194,3 @@ class options(optparse.Values):
     write_driver_array = "write_driver_array"
     write_driver = "write_driver"
     write_mask_and_array = "write_mask_and_array"
-
-    # Non-public options
-    experimental_power = True

compiler/tests/20_sram_1bank_16mux_test.py

@@ -22,9 +22,19 @@ class sram_1bank_8mux_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=2,
                         num_words=256,
-                        num_banks=1)
+                        num_banks=1,
+                        num_spare_cols=num_spare_cols,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row=16
         c.recompute_sizes()

compiler/tests/20_sram_1bank_2mux_global_test.py

@@ -23,9 +23,19 @@ class sram_1bank_2mux_global_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
         OPTS.local_array_size = 8
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=8,
                         num_words=32,
-                        num_banks=1)
+                        num_banks=1,
+                        num_spare_cols=num_spare_cols,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row=2
         c.recompute_sizes()

compiler/tests/20_sram_1bank_2mux_test.py

@@ -22,9 +22,19 @@ class sram_1bank_2mux_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=4,
                         num_words=32,
-                        num_banks=1)
+                        num_banks=1,
+                        num_spare_cols=num_spare_cols,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row=2
         c.recompute_sizes()

compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py

@@ -22,11 +22,20 @@ class sram_1bank_2mux_wmask_spare_cols_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=8,
                         write_size=4,
-                        num_spare_cols=3,
                         num_words=64,
-                        num_banks=1)
+                        num_banks=1,
+                        num_spare_cols=num_spare_cols+2,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row = 2
         c.recompute_sizes()

compiler/tests/20_sram_1bank_2mux_wmask_test.py

@@ -22,10 +22,20 @@ class sram_1bank_2mux_wmask_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=8,
                         write_size=4,
                         num_words=64,
-                        num_banks=1)
+                        num_banks=1,
+                        num_spare_cols=num_spare_cols,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row = 2
         c.recompute_sizes()

compiler/tests/20_sram_1bank_32b_1024_wmask_test.py

@@ -23,10 +23,20 @@ class sram_1bank_32b_1024_wmask_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=1024,
-                        num_banks=1)
+                        num_banks=1,
+                        num_spare_cols=num_spare_cols,
+                        num_spare_rows=num_spare_rows)
 
         c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w sram "

compiler/tests/20_sram_1bank_4mux_test.py

@@ -22,9 +22,19 @@ class sram_1bank_4mux_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=4,
                         num_words=64,
-                        num_banks=1)
+                        num_banks=1,
+                        num_spare_cols=num_spare_cols,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row=4
         c.recompute_sizes()

compiler/tests/20_sram_1bank_8mux_test.py

@@ -22,9 +22,19 @@ class sram_1bank_8mux_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=2,
                         num_words=128,
-                        num_banks=1)
+                        num_banks=1,
+                        num_spare_cols=num_spare_cols,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row=8
         c.recompute_sizes()

compiler/tests/20_sram_1bank_nomux_spare_cols_test.py

@@ -22,10 +22,19 @@ class sram_1bank_nomux_spare_cols_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=8,
-                        num_spare_cols=3,
                         num_words=16,
-                        num_banks=1)
+                        num_banks=1,
+                        num_spare_cols=num_spare_cols+2,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row = 1
         c.recompute_sizes()

compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py

@@ -23,11 +23,20 @@ class sram_1bank_nomux_wmask_sparecols_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=8,
                         write_size=4,
                         num_words=16,
-                        num_spare_cols=3,
+                        num_banks=1,
-                        num_banks=1)
+                        num_spare_cols=num_spare_cols+2,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row = 1
         c.recompute_sizes()

compiler/tests/20_sram_1bank_nomux_wmask_test.py

@@ -22,10 +22,20 @@ class sram_1bank_nomux_wmask_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=8,
                         write_size=4,
                         num_words=16,
-                        num_banks=1)
+                        num_banks=1,
+                        num_spare_cols=num_spare_cols+2,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row = 1
         c.recompute_sizes()

technology/sky130/modules/sky130_bitcell_array.py

@@ -63,10 +63,7 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
                     row_layout.append(self.cell2)
                     self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
                                                            mod=self.cell2)
-                if col % 2 == 1:
+                self.connect_inst(self.get_bitcell_pins(row, col))
-                    self.connect_inst(self.get_bitcell_pins(row, col, swap=True))
-                else:
-                    self.connect_inst(self.get_bitcell_pins(row, col, swap=False))
                 if col != self.column_size - 1:
                     if alternate_strap:
                         if row % 2:

technology/sky130/modules/sky130_bitcell_base_array.py

@@ -69,14 +69,6 @@ class sky130_bitcell_base_array(bitcell_base_array):
         bitcell_pins = []
         for port in self.all_ports:
             bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
-        if swap:
-            swap_pins = []
-            for pin in bitcell_pins:
-                if "bl" in pin:
-                    swap_pins.append(pin.replace("bl", "br"))
-                elif "br" in pin:
-                    swap_pins.append(pin.replace("br", "bl"))
-            bitcell_pins = swap_pins
         bitcell_pins.append("gnd") # gnd
         bitcell_pins.append("vdd") # vdd
         bitcell_pins.append("vdd") # vpb

technology/sky130/modules/sky130_col_cap_array.py

@@ -89,10 +89,10 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
             elif col % 4 == 2:
                 row_layout.append(self.colend1)
                 self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
-                pins.append("fake_br_{}".format(bitline))
+                pins.append("fake_bl_{}".format(bitline))
                 pins.append("vdd")
                 pins.append("gnd")
-                pins.append("fake_bl_{}".format(bitline))
+                pins.append("fake_br_{}".format(bitline))
                 pins.append("gate")
                 bitline += 1
             elif col % 4 ==3:
@@ -194,7 +194,7 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
 
                 elif col % 4 == 2:
                     pin = self.cell_inst[col].get_pin("bl")
-                    text = "fake_br_{}".format(int(col/2))
+                    text = "fake_bl_{}".format(int(col/2))
                     self.add_layout_pin(text=text,
                             layer=pin.layer,
                             offset=pin.ll().scale(1, 0),
@@ -202,7 +202,7 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
                             height=pin.height())
                     
                     pin = self.cell_inst[col].get_pin("br")
-                    text = "fake_bl_{}".format(int(col/2))
+                    text = "fake_br_{}".format(int(col/2))
                     self.add_layout_pin(text=text,
                             layer=pin.layer,
                             offset=pin.ll().scale(1, 0),

technology/sky130/modules/sky130_dummy_array.py

@@ -72,11 +72,7 @@ class sky130_dummy_array(sky130_bitcell_base_array):
                     row_layout.append(self.dummy_cell2)
                     self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
                                                            mod=self.dummy_cell2)
-                if col % 2 == 1:
+                self.connect_inst(self.get_bitcell_pins(row, col))
-                    self.connect_inst(self.get_bitcell_pins(row, col, swap=True))
-                else:
-                    self.connect_inst(self.get_bitcell_pins(row, col, swap=False))
-                #self.connect_inst(self.get_bitcell_pins(row, col))
                 if col != self.column_size - 1:
                     if alternate_strap:
                         if col % 2:
@@ -129,8 +125,6 @@ class sky130_dummy_array(sky130_bitcell_base_array):
             for port in self.all_ports:
                 bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
                 text = "bl_{0}_{1}".format(port, col)
-                if "Y" in self.cell_inst[0, col].mirror:
-                    text = text.replace("bl", "br")
                 self.add_layout_pin(text=text,
                                     layer=bl_pin.layer,
                                     offset=bl_pin.ll().scale(1, 0),
@@ -138,8 +132,6 @@ class sky130_dummy_array(sky130_bitcell_base_array):
                                     height=self.height)
                 br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
                 text = "br_{0}_{1}".format(port, col)
-                if "Y" in self.cell_inst[0, col].mirror:
-                    text = text.replace("br", "bl")
                 self.add_layout_pin(text=text,
                                     layer=br_pin.layer,
                                     offset=br_pin.ll().scale(1, 0),