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port data routing fix

This commit is contained in:
Joey Kunzler 2020-04-29 15:48:15 -07:00
parent 0bae652be9
commit 1b6634bb97
2 changed files with 24 additions and 14 deletions
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15
compiler/base/hierarchy_layout.py
View File

@ -905,8 +905,11 @@ class layout():
max_x = max([pin.center().x for pin in pins]) max_x = max([pin.center().x for pin in pins])
min_x = min([pin.center().x for pin in pins]) min_x = min([pin.center().x for pin in pins])
max_x_lc = max([pin.lc().x for pin in pins])
min_x_rc = min([pin.rc().x for pin in pins])
# if we are less than a pitch, just create a non-preferred layer jog # if we are less than a pitch, just create a non-preferred layer jog
if max_x-min_x <= pitch: if max_x - min_x <= pitch:
half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)] half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)]
# Add the horizontal trunk on the vertical layer! # Add the horizontal trunk on the vertical layer!
@ -927,6 +930,14 @@ class layout():
# Route each pin to the trunk # Route each pin to the trunk
for pin in pins: for pin in pins:
# If there is sufficient space, Route from the edge of the pins
# Otherwise, route from the center of the pins
if max_x_lc - min_x_rc > pitch:
if pin.center().x == max_x:
mid = vector(pin.lc().x, trunk_offset.y)
else:
mid = vector(pin.rc().x, trunk_offset.y)
else:
mid = vector(pin.center().x, trunk_offset.y) mid = vector(pin.center().x, trunk_offset.y)
self.add_path(self.vertical_layer, [pin.center(), mid]) self.add_path(self.vertical_layer, [pin.center(), mid])
self.add_via_center(layers=layer_stack, self.add_via_center(layers=layer_stack,
@ -1095,7 +1106,7 @@ class layout():
# list of routes to do # list of routes to do
while vcg: while vcg:
# from pprint import pformat # from pprint import pformat
# print("VCG:\n",pformat(vcg)) # print("VCG:\n", pformat(vcg))
# get a route from conflict graph with empty fanout set # get a route from conflict graph with empty fanout set
net_name = None net_name = None
for net_name, conflicts in vcg.items(): for net_name, conflicts in vcg.items():

3
compiler/modules/port_data.py
View File

@ -521,7 +521,7 @@ class port_data(design.design):
insn2_start_bit = 1 if self.port == 0 else 0 insn2_start_bit = 1 if self.port == 0 else 0
self.connect_bitlines(inst1=inst1, self.channel_route_bitlines(inst1=inst1,
inst2=inst2, inst2=inst2,
num_bits=self.num_cols, num_bits=self.num_cols,
inst2_start_bit=insn2_start_bit) inst2_start_bit=insn2_start_bit)
@ -743,4 +743,3 @@ class port_data(design.design):
"""Precharge adds a loop between bitlines, can be excluded to reduce complexity""" """Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
if self.precharge_array_inst: if self.precharge_array_inst:
self.graph_inst_exclude.add(self.precharge_array_inst) self.graph_inst_exclude.add(self.precharge_array_inst)