fix vnb and vpb routing in rba

compiler/base/custom_cell_properties.py

@@ -93,9 +93,9 @@ class cell:
         # It is assumed it is [nwell, pwell]
         self._body_bias = body_bias
         self._port_map['vnb'] = body_bias[0]
-        self._port_types['vnb'] = "POWER"
+        self._port_types['vnb'] = "GROUND"
         self._port_map['vpb'] = body_bias[1]
-        self._port_types['vpb'] = "GROUND"
+        self._port_types['vpb'] = "POWER"
         
     @property
     def port_types(self):

compiler/gdsMill/gdsMill/vlsiLayout.py

@@ -770,7 +770,13 @@ class VlsiLayout:
                 from tech import layer_override
                 if layer_override[label_text]:
                     shapes = self.getAllShapes((layer_override[label_text][0], None))
+                    if not shapes:
+                        shapes = self.getAllShapes(lpp)
+                    else:
                         lpp = layer_override[label_text]
+                        
+                        
+                    
             except:
                 pass
             for boundary in shapes:

compiler/modules/bank.py

@@ -620,7 +620,7 @@ class bank(design.design):
             self.copy_power_pins(inst, "gnd", add_vias=False)
 
         if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
-            for pin_name, supply_name in zip(['vpb','vnb'],['gnd','vdd']):
+            for pin_name, supply_name in zip(['vnb','vpb'],['gnd','vdd']):
                 self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name)
 
         # If we use the pinvbuf as the decoder, we need to add power pins.