fix vnb and vpb routing in rba

This commit is contained in:
Jesse Cirimelli-Low 2021-07-08 18:31:55 -07:00
parent b5daa51a6c
commit 1a7adcfdad
3 changed files with 10 additions and 4 deletions

View File

@ -93,9 +93,9 @@ class cell:
# It is assumed it is [nwell, pwell] # It is assumed it is [nwell, pwell]
self._body_bias = body_bias self._body_bias = body_bias
self._port_map['vnb'] = body_bias[0] self._port_map['vnb'] = body_bias[0]
self._port_types['vnb'] = "POWER" self._port_types['vnb'] = "GROUND"
self._port_map['vpb'] = body_bias[1] self._port_map['vpb'] = body_bias[1]
self._port_types['vpb'] = "GROUND" self._port_types['vpb'] = "POWER"
@property @property
def port_types(self): def port_types(self):

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@ -770,7 +770,13 @@ class VlsiLayout:
from tech import layer_override from tech import layer_override
if layer_override[label_text]: if layer_override[label_text]:
shapes = self.getAllShapes((layer_override[label_text][0], None)) shapes = self.getAllShapes((layer_override[label_text][0], None))
lpp = layer_override[label_text] if not shapes:
shapes = self.getAllShapes(lpp)
else:
lpp = layer_override[label_text]
except: except:
pass pass
for boundary in shapes: for boundary in shapes:

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@ -620,7 +620,7 @@ class bank(design.design):
self.copy_power_pins(inst, "gnd", add_vias=False) self.copy_power_pins(inst, "gnd", add_vias=False)
if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins: if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
for pin_name, supply_name in zip(['vpb','vnb'],['gnd','vdd']): for pin_name, supply_name in zip(['vnb','vpb'],['gnd','vdd']):
self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name) self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name)
# If we use the pinvbuf as the decoder, we need to add power pins. # If we use the pinvbuf as the decoder, we need to add power pins.