mirror of https://github.com/VLSIDA/OpenRAM.git
remove references to bank_sel
This commit is contained in:
Bugra Onal
parent
242d90f543
commit
1a23d156c0
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@ -1,313 +0,0 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from tech import drc
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from base import design
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from base import vector
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from pgates import pinv
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from pgates import pnand2
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from pgates import pnor2
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from sram_factory import factory
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from globals import OPTS
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class bank_select(design):
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"""Create a bank select signal that is combined with an array of
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NOR+INV gates to gate the control signals in case of multiple
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banks are created in upper level SRAM module
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"""
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def __init__(self, name="bank_select", port="rw"):
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super().__init__(name)
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self.port = port
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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self.create_instances()
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def create_layout(self):
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self.calculate_module_offsets()
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self.place_instances()
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self.route_instances()
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self.height = max([x.uy() for x in self.inv_inst]) + self.m1_width
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self.width = max([x.rx() for x in self.inv_inst])
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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# Number of control lines in the bus
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if self.port == "rw":
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self.num_control_lines = 4
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else:
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self.num_control_lines = 3
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# The order of the control signals on the control bus:
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# FIXME: Update for multiport (these names are not right)
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self.input_control_signals = ["clk_buf", "clk_buf_bar"]
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if (self.port == "rw") or (self.port == "w"):
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self.input_control_signals.append("w_en")
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if (self.port == "rw") or (self.port == "r"):
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self.input_control_signals.append("s_en")
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# These will be outputs of the gaters if this is multibank
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self.control_signals = ["gated_" + str for str in self.input_control_signals]
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self.add_pin_list(self.input_control_signals, "INPUT")
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self.add_pin("bank_sel")
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self.add_pin_list(self.control_signals, "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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""" Create modules for later instantiation """
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self.dff = factory.create(module_type="dff")
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height = self.dff.height + drc("poly_to_active")
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# 1x Inverter
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self.inv_sel = factory.create(module_type="pinv", height=height)
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# 4x Inverter
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self.inv4x = factory.create(module_type="pinv", height=height, size=4)
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self.nor2 = factory.create(module_type="pnor2", height=height)
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self.inv4x_nor = factory.create(module_type="pinv", height=height, size=4)
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self.nand2 = factory.create(module_type="pnand2", height=height)
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def calculate_module_offsets(self):
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self.xoffset_nand = self.inv4x.width + 3 * self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_nor = self.inv4x.width + 3 * self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_bank_sel_inv = 0
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self.xoffset_inputs = 0
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self.yoffset_maxpoint = self.num_control_lines * self.inv4x.height
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def create_instances(self):
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self.bank_sel_inv=self.add_inst(name="bank_sel_inv",
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mod=self.inv_sel)
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self.connect_inst(["bank_sel", "bank_sel_bar", "vdd", "gnd"])
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self.logic_inst = []
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self.inv_inst = []
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for i in range(self.num_control_lines):
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input_name = self.input_control_signals[i]
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gated_name = self.control_signals[i]
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name_nand = "nand_{}".format(input_name)
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name_nor = "nor_{}".format(input_name)
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name_inv = "inv_{}".format(input_name)
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# These require OR (nor2+inv) gates since they are active low.
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# (writes occur on clk low)
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if input_name in ("clk_buf"):
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self.logic_inst.append(self.add_inst(name=name_nor,
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mod=self.nor2))
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self.connect_inst([input_name,
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"bank_sel_bar",
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gated_name + "_temp_bar",
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"vdd",
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"gnd"])
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# They all get inverters on the output
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self.inv_inst.append(self.add_inst(name=name_inv,
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mod=self.inv4x_nor))
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self.connect_inst([gated_name + "_temp_bar",
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gated_name,
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"vdd",
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"gnd"])
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# the rest are AND (nand2+inv) gates
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else:
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self.logic_inst.append(self.add_inst(name=name_nand,
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mod=self.nand2))
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self.connect_inst([input_name,
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"bank_sel",
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gated_name + "_temp_bar",
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"vdd",
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"gnd"])
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# They all get inverters on the output
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self.inv_inst.append(self.add_inst(name=name_inv,
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mod=self.inv4x))
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self.connect_inst([gated_name + "_temp_bar",
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gated_name,
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"vdd",
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"gnd"])
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def place_instances(self):
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# bank select inverter
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self.bank_select_inv_position = vector(self.xoffset_bank_sel_inv, 0)
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# bank select inverter (must be made unique if more than one OR)
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self.bank_sel_inv.place(vector(self.xoffset_bank_sel_inv, 0))
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for i in range(self.num_control_lines):
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logic_inst = self.logic_inst[i]
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inv_inst = self.inv_inst[i]
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input_name = self.input_control_signals[i]
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if i == 0:
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y_offset = 0
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else:
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y_offset = self.inv4x_nor.height + self.inv4x.height * (i - 1)
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if i % 2:
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y_offset += self.inv4x.height
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mirror = "MX"
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else:
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mirror = ""
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# These require OR (nor2+inv) gates since they are active low.
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# (writes occur on clk low)
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if input_name in ("clk_buf"):
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logic_inst.place(offset=[self.xoffset_nor, y_offset],
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mirror=mirror)
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# the rest are AND (nand2+inv) gates
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else:
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logic_inst.place(offset=[self.xoffset_nand, y_offset],
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mirror=mirror)
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# They all get inverters on the output
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inv_inst.place(offset=[logic_inst.rx(), y_offset],
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mirror=mirror)
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def route_instances(self):
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# bank_sel is vertical wire
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bank_sel_inv_pin = self.bank_sel_inv.get_pin("A")
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xoffset_bank_sel = bank_sel_inv_pin.lx()
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bank_sel_line_pos = vector(xoffset_bank_sel, 0)
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bank_sel_line_end = vector(xoffset_bank_sel, self.yoffset_maxpoint)
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self.add_path("m2", [bank_sel_line_pos, bank_sel_line_end])
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self.add_via_center(layers=self.m1_stack,
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offset=bank_sel_inv_pin.center())
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# Route the pin to the left edge as well
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bank_sel_pin_pos=vector(0, 0)
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bank_sel_pin_end=vector(bank_sel_line_pos.x, bank_sel_pin_pos.y)
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self.add_layout_pin_segment_center(text="bank_sel",
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layer="m3",
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start=bank_sel_pin_pos,
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end=bank_sel_pin_end)
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self.add_via_center(layers=self.m2_stack,
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offset=bank_sel_pin_end,
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directions=("H", "H"))
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# bank_sel_bar is vertical wire
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bank_sel_bar_pin = self.bank_sel_inv.get_pin("Z")
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xoffset_bank_sel_bar = bank_sel_bar_pin.rx()
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self.add_label_pin(text="bank_sel_bar",
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layer="m2",
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offset=vector(xoffset_bank_sel_bar, 0),
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height=self.inv4x.height)
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self.add_via_center(layers=self.m1_stack,
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offset=bank_sel_bar_pin.rc())
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for i in range(self.num_control_lines):
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logic_inst = self.logic_inst[i]
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inv_inst = self.inv_inst[i]
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input_name = self.input_control_signals[i]
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gated_name = self.control_signals[i]
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if input_name in ("clk_buf"):
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xoffset_bank_signal = xoffset_bank_sel_bar
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else:
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xoffset_bank_signal = xoffset_bank_sel
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# Connect the logic output to inverter input
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out_pin = logic_inst.get_pin("Z")
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out_pos = out_pin.center()
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in_pin = inv_inst.get_pin("A")
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in_pos = in_pin.center()
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mid1_pos = vector(0.5 * (out_pos.x + in_pos.x), out_pos.y)
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mid2_pos = vector(0.5 * (out_pos.x + in_pos.x), in_pos.y)
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self.add_path("m1", [out_pos, mid1_pos, mid2_pos, in_pos])
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# Connect the logic B input to bank_sel / bank_sel_bar
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logic_pin = logic_inst.get_pin("B")
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logic_pos = logic_pin.center()
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input_pos = vector(xoffset_bank_signal, logic_pos.y)
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self.add_path("m3", [logic_pos, input_pos])
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self.add_via_center(self.m2_stack,
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input_pos)
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self.add_via_stack_center(from_layer=logic_pin.layer,
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to_layer="m3",
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offset=logic_pos)
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# Connect the logic A input to the input pin
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logic_pin = logic_inst.get_pin("A")
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logic_pos = logic_pin.center()
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input_pos = vector(0, logic_pos.y)
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self.add_via_stack_center(from_layer=logic_pin.layer,
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to_layer="m3",
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offset=logic_pos)
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self.add_layout_pin_segment_center(text=input_name,
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layer="m3",
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start=input_pos,
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end=logic_pos)
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# Add output pins
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out_pin = inv_inst.get_pin("Z")
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self.add_layout_pin(text=gated_name,
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layer=out_pin.layer,
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offset=out_pin.ll(),
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width=inv_inst.rx() - out_pin.lx(),
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height=out_pin.height())
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# Find the x offsets for where the vias/pins should be placed
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a_xoffset = self.logic_inst[0].lx()
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b_xoffset = self.inv_inst[0].lx()
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for num in range(self.num_control_lines):
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# Route both supplies
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for n in ["vdd", "gnd"]:
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supply_pin = self.inv_inst[num].get_pin(n)
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supply_offset = supply_pin.ll().scale(0, 1)
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self.add_rect(layer="m1",
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offset=supply_offset,
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width=self.width)
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# Add pins in two locations
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for xoffset in [a_xoffset, b_xoffset]:
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pin_pos = vector(xoffset, supply_pin.cy())
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self.add_via_center(layers=self.m1_stack,
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offset=pin_pos,
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directions=("H", "H"))
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self.add_via_center(layers=self.m2_stack,
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offset=pin_pos,
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directions=("H", "H"))
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self.add_layout_pin_rect_center(text=n,
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layer="m3",
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offset=pin_pos)
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# Add vdd/gnd supply rails
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gnd_pin = self.inv_inst[num].get_pin("gnd")
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left_gnd_pos = vector(0, gnd_pin.cy())
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self.add_layout_pin_segment_center(text="gnd",
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layer="m1",
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start=left_gnd_pos,
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end=gnd_pin.rc())
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vdd_pin = self.inv_inst[num].get_pin("vdd")
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left_vdd_pos = vector(0, vdd_pin.cy())
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self.add_layout_pin_segment_center(text="vdd",
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layer="m1",
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start=left_vdd_pos,
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end=vdd_pin.rc())
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@ -426,13 +426,6 @@ class sram_1bank(design, verilog, lef):
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names=self.addr_bus_names,
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names=self.addr_bus_names,
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length=self.addr_bus_height))
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length=self.addr_bus_height))
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self.bank_sel_bus_names = ["bank_sel{0}_{1}".format(port, i) for i in range(1)]#range(self.num_banks)]
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self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2",
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pitch=self.m2_pitch,
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offset=self.bank_sel_bus_offset,
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names=self.bank_sel_bus_names,
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length=self.vertical_bus_height))
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# Horizontal data bus
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# Horizontal data bus
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self.data_bus_names = ["DATA{0}[{1}]".format(port, i) for i in range(self.word_size)]
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self.data_bus_names = ["DATA{0}[{1}]".format(port, i) for i in range(self.word_size)]
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self.data_bus_positions = self.create_horizontal_pin_bus(layer="m3",
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self.data_bus_positions = self.create_horizontal_pin_bus(layer="m3",
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@ -462,16 +455,6 @@ class sram_1bank(design, verilog, lef):
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names=self.control_bus_names[port],
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names=self.control_bus_names[port],
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length=self.control_bus_width))
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length=self.control_bus_width))
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def add_multi_bank_modules(self):
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""" Create the multibank address flops and bank decoder """
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from dff_buf_array import dff_buf_array
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self.msb_address = dff_buf_array(name="msb_address",
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rows=1,
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columns=self.num_banks / 2)
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if self.num_banks>2:
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self.msb_decoder = self.bank.decoder.pre2_4
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def add_modules(self):
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def add_modules(self):
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self.bitcell = factory.create(module_type=OPTS.bitcell)
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self.bitcell = factory.create(module_type=OPTS.bitcell)
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self.dff = factory.create(module_type="dff")
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self.dff = factory.create(module_type="dff")
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@ -542,9 +525,6 @@ class sram_1bank(design, verilog, lef):
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for port in self.all_ports:
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for port in self.all_ports:
|
||||||
for bit in range(self.bank_addr_size):
|
for bit in range(self.bank_addr_size):
|
||||||
temp.append("a{0}_{1}".format(port, bit))
|
temp.append("a{0}_{1}".format(port, bit))
|
||||||
# if(self.num_banks > 1):
|
|
||||||
# for port in self.all_ports:
|
|
||||||
# temp.append("bank_sel{0}_{1}".format(port, bank_num))
|
|
||||||
for port in self.read_ports:
|
for port in self.read_ports:
|
||||||
temp.append("s_en{0}".format(port))
|
temp.append("s_en{0}".format(port))
|
||||||
for port in self.all_ports:
|
for port in self.all_ports:
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue