Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport.

compiler/modules/bank_select.py

@@ -62,16 +62,26 @@ class bank_select(design.design):
 
     def add_modules(self):
         """ Create modules for later instantiation """
+        from importlib import reload
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
+        self.bitcell = self.mod_bitcell()
+        
+        height = self.bitcell.height + drc["poly_to_active"]
+
         # 1x Inverter
-        self.inv = pinv()
+        self.inv_sel = pinv(height=height)
-        self.add_mod(self.inv)
+        self.add_mod(self.inv_sel)
 
         # 4x Inverter
-        self.inv4x = pinv(4)
+        self.inv = self.inv4x = pinv(4)
         self.add_mod(self.inv4x)
 
-        self.nor2 = pnor2()
+        self.nor2 = pnor2(height=height)
         self.add_mod(self.nor2)
+        
+        self.inv4x_nor = pinv(size=4, height=height)
+        self.add_mod(self.inv4x_nor)
 
         self.nand2 = pnand2()
         self.add_mod(self.nand2)
@@ -92,7 +102,7 @@ class bank_select(design.design):
     def create_modules(self):
         
         self.bank_sel_inv=self.add_inst(name="bank_sel_inv", 
-                                        mod=self.inv)
+                                        mod=self.inv_sel)
         self.connect_inst(["bank_sel", "bank_sel_bar", "vdd", "gnd"])
 
         self.logic_inst = []
@@ -116,6 +126,14 @@ class bank_select(design.design):
                                    "vdd",
                                    "gnd"])
                 
+                # They all get inverters on the output
+                self.inv_inst.append(self.add_inst(name=name_inv, 
+                                                   mod=self.inv4x_nor))
+                self.connect_inst([gated_name+"_temp_bar",
+                                   gated_name,
+                                   "vdd",
+                                   "gnd"])
+                
             # the rest are AND (nand2+inv) gates
             else:
                 self.logic_inst.append(self.add_inst(name=name_nand, 
@@ -126,13 +144,13 @@ class bank_select(design.design):
                                    "vdd",
                                    "gnd"])
 
-            # They all get inverters on the output
+                # They all get inverters on the output
-            self.inv_inst.append(self.add_inst(name=name_inv, 
+                self.inv_inst.append(self.add_inst(name=name_inv, 
-                                               mod=self.inv4x))
+                                                   mod=self.inv4x))
-            self.connect_inst([gated_name+"_temp_bar",
+                self.connect_inst([gated_name+"_temp_bar",
-                               gated_name,
+                                   gated_name,
-                               "vdd",
+                                   "vdd",
-                               "gnd"])
+                                   "gnd"])
 
     def place_modules(self):
         
@@ -149,7 +167,11 @@ class bank_select(design.design):
             
             input_name = self.input_control_signals[i]
 
-            y_offset = self.inv.height * i
+            if i == 0:
+                y_offset = 0
+            else:
+                y_offset = self.inv4x_nor.height + self.inv.height * (i-1)
+            
             if i%2:
                 y_offset += self.inv.height
                 mirror = "MX"

compiler/tests/19_bank_select_test.py

@@ -21,6 +21,15 @@ class bank_select_test(openram_test):
         a = bank_select.bank_select(port="rw")
         self.local_check(a)
         
+        OPTS.bitcell = "pbitcell"
+        debug.info(1, "No column mux, rw control logic")
+        a = bank_select.bank_select(port="rw")
+        self.local_check(a)
+        
+        OPTS.num_rw_ports = 0
+        OPTS.num_w_ports = 1
+        OPTS.num_r_ports = 1
+
         debug.info(1, "No column mux, w control logic")
         a = bank_select.bank_select(port="w")
         self.local_check(a)

compiler/tests/19_pmulti_bank_test.py

@@ -0,0 +1,61 @@
+#!/usr/bin/env python3
+"""
+Run a regression test on various srams
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+import debug
+
+class multi_bank_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        from bank import bank
+        from sram_config import sram_config
+        OPTS.bitcell = "pbitcell"
+
+        # testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent)
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        c = sram_config(word_size=4,
+                        num_words=16)
+        c.num_banks=2
+
+        c.words_per_row=1
+        debug.info(1, "No column mux")
+        a = bank(c, name="bank1_multi")
+        self.local_check(a)
+
+        c.num_words=32
+        c.words_per_row=2
+        debug.info(1, "Two way column mux")
+        a = bank(c, name="bank2_multi")
+        self.local_check(a)
+
+        c.num_words=64
+        c.words_per_row=4
+        debug.info(1, "Four way column mux")
+        a = bank(c, name="bank3_multi")
+        self.local_check(a)
+
+        c.word_size=2
+        c.num_words=128
+        c.words_per_row=8
+        debug.info(1, "Eight way column mux")
+        a = bank(c, name="bank4_multi")
+        self.local_check(a)
+        
+        globals.end_openram()
+        
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()