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Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport.

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This commit is contained in:
Michael Timothy Grimes
2018-09-27 02:01:32 -07:00
parent 1ca0154027
commit 19d68f613e
3 changed files with 105 additions and 13 deletions
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compiler/modules/bank_select.py
+35 -13
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@@ -62,16 +62,26 @@ class bank_select(design.design):
def add_modules(self):
""" Create modules for later instantiation """
from importlib import reload
c = reload(__import__(OPTS.bitcell))
self.mod_bitcell = getattr(c, OPTS.bitcell)
self.bitcell = self.mod_bitcell()
height = self.bitcell.height + drc["poly_to_active"]
# 1x Inverter
self.inv = pinv()
self.add_mod(self.inv)
self.inv_sel = pinv(height=height)
self.add_mod(self.inv_sel)
# 4x Inverter
self.inv4x = pinv(4)
self.inv = self.inv4x = pinv(4)
self.add_mod(self.inv4x)
self.nor2 = pnor2()
self.nor2 = pnor2(height=height)
self.add_mod(self.nor2)
self.inv4x_nor = pinv(size=4, height=height)
self.add_mod(self.inv4x_nor)
self.nand2 = pnand2()
self.add_mod(self.nand2)
@@ -92,7 +102,7 @@ class bank_select(design.design):
def create_modules(self):
self.bank_sel_inv=self.add_inst(name="bank_sel_inv",
mod=self.inv)
mod=self.inv_sel)
self.connect_inst(["bank_sel", "bank_sel_bar", "vdd", "gnd"])
self.logic_inst = []
@@ -116,6 +126,14 @@ class bank_select(design.design):
"vdd",
"gnd"])
# They all get inverters on the output
self.inv_inst.append(self.add_inst(name=name_inv,
mod=self.inv4x_nor))
self.connect_inst([gated_name+"_temp_bar",
gated_name,
"vdd",
"gnd"])
# the rest are AND (nand2+inv) gates
else:
self.logic_inst.append(self.add_inst(name=name_nand,
@@ -126,13 +144,13 @@ class bank_select(design.design):
"vdd",
"gnd"])
# They all get inverters on the output
self.inv_inst.append(self.add_inst(name=name_inv,
mod=self.inv4x))
self.connect_inst([gated_name+"_temp_bar",
gated_name,
"vdd",
"gnd"])
# They all get inverters on the output
self.inv_inst.append(self.add_inst(name=name_inv,
mod=self.inv4x))
self.connect_inst([gated_name+"_temp_bar",
gated_name,
"vdd",
"gnd"])
def place_modules(self):
@@ -149,7 +167,11 @@ class bank_select(design.design):
input_name = self.input_control_signals[i]
y_offset = self.inv.height * i
if i == 0:
y_offset = 0
else:
y_offset = self.inv4x_nor.height + self.inv.height * (i-1)
if i%2:
y_offset += self.inv.height
mirror = "MX"