mirror of https://github.com/VLSIDA/OpenRAM.git
Must over-ride build_graph in dummy bitcell.
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@ -26,3 +26,7 @@ class sky130_dummy_bitcell(bitcell_base):
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cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy"
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cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy"
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super().__init__(name, cell_name, prop=props.bitcell_1port)
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super().__init__(name, cell_name, prop=props.bitcell_1port)
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debug.info(2, "Create dummy bitcell")
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debug.info(2, "Create dummy bitcell")
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def build_graph(self, graph, inst_name, port_nets):
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""" Adds edges based on inputs/outputs. Overrides base class function. """
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pass
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