mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 01:24:39 +02:00
Use custom cells when needed.
This commit is contained in:
mrg
@@ -0,0 +1,147 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from vector import vector
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import design
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from sram_factory import factory
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from globals import OPTS
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from tech import layer
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class and2_dec(design.design):
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"""
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This is an AND with configurable drive strength.
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"""
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def __init__(self, name, size=1, height=None, add_wells=True):
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design.design.__init__(self, name)
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debug.info(1, "Creating and2_dec {}".format(name))
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self.add_comment("size: {}".format(size))
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self.size = size
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self.height = height
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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self.nand = factory.create(module_type="nand2_dec",
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height=self.height)
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self.inv = factory.create(module_type="inv_dec",
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height=self.height,
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size=self.size)
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self.add_mod(self.nand)
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self.add_mod(self.inv)
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def create_layout(self):
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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self.width = self.nand.width + self.inv.width
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self.height = self.nand.height
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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self.route_supply_rails()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin("A", "INPUT")
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self.add_pin("B", "INPUT")
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self.add_pin("Z", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_insts(self):
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self.nand_inst = self.add_inst(name="pand2_dec_nand",
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mod=self.nand)
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self.connect_inst(["A", "B", "zb_int", "vdd", "gnd"])
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self.inv_inst = self.add_inst(name="pand2_dec_inv",
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mod=self.inv)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add NAND to the right
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self.nand_inst.place(offset=vector(0, 0))
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# Add INV to the right
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self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0))
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top, (middle), and bottom. """
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if OPTS.tech_name == "sky130":
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for name in ["vdd", "gnd"]:
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for inst in [self.nand_inst, self.inv_inst]:
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self.copy_layout_pin(inst, name)
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else:
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self.add_layout_pin_rect_center(text="gnd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, 0),
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width=self.width)
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self.add_layout_pin_rect_center(text="vdd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, self.height),
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width=self.width)
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def add_wires(self):
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# nand Z to inv A
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z1_pin = self.nand_inst.get_pin("Z")
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a2_pin = self.inv_inst.get_pin("A")
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if OPTS.tech_name == "sky130":
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mid1_point = vector(a2_pin.cx(), z1_pin.cy())
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else:
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mid1_point = vector(z1_pin.cx(), a2_pin.cy())
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self.add_path(self.route_layer,
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[z1_pin.center(), mid1_point, a2_pin.center()])
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def add_layout_pins(self):
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pin = self.inv_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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for pin_name in ["A", "B"]:
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pin = self.nand_inst.get_pin(pin_name)
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self.add_layout_pin_rect_center(text=pin_name,
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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def get_stage_efforts(self, external_cout, inp_is_rise=False):
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"""Get the stage efforts of the A or B -> Z path"""
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stage_effort_list = []
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stage1_cout = self.inv.get_cin()
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stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise)
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stage_effort_list.append(stage1)
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last_stage_is_rise = stage1.is_rise
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stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise)
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stage_effort_list.append(stage2)
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return stage_effort_list
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def get_cin(self):
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"""Return the relative input capacitance of a single input"""
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return self.nand.get_cin()
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@@ -0,0 +1,156 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from vector import vector
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import design
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from sram_factory import factory
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from globals import OPTS
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from tech import layer
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class and3_dec(design.design):
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"""
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This is an AND with configurable drive strength.
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"""
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def __init__(self, name, size=1, height=None, add_wells=True):
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design.design.__init__(self, name)
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debug.info(1, "Creating and3_dec {}".format(name))
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self.add_comment("size: {}".format(size))
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self.size = size
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self.height = height
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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self.nand = factory.create(module_type="nand3_dec",
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height=self.height)
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self.inv = factory.create(module_type="inv_dec",
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height=self.height,
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size=self.size)
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self.add_mod(self.nand)
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self.add_mod(self.inv)
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def create_layout(self):
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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self.width = self.nand.width + self.inv.width
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self.height = self.nand.height
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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self.route_supply_rails()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin("A", "INPUT")
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self.add_pin("B", "INPUT")
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self.add_pin("C", "INPUT")
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self.add_pin("Z", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_insts(self):
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self.nand_inst = self.add_inst(name="pand3_dec_nand",
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mod=self.nand)
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self.connect_inst(["A", "B", "C", "zb_int", "vdd", "gnd"])
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self.inv_inst = self.add_inst(name="pand3_dec_inv",
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mod=self.inv)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add NAND to the right
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self.nand_inst.place(offset=vector(0, 0))
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# Add INV to the right
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self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0))
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top, (middle), and bottom. """
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if OPTS.tech_name == "sky130":
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for name in ["vdd", "gnd"]:
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for inst in [self.nand_inst, self.inv_inst]:
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self.copy_layout_pin(inst, name)
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else:
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self.add_layout_pin_rect_center(text="gnd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, 0),
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width=self.width)
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self.add_layout_pin_rect_center(text="vdd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, self.height),
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width=self.width)
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def add_wires(self):
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# nand Z to inv A
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z1_pin = self.nand_inst.get_pin("Z")
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a2_pin = self.inv_inst.get_pin("A")
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if OPTS.tech_name == "sky130":
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mid1_point = vector(a2_pin.cx(), z1_pin.cy())
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else:
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mid1_point = vector(z1_pin.cx(), a2_pin.cy())
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self.add_path(self.route_layer,
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[z1_pin.center(), mid1_point, a2_pin.center()])
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def add_layout_pins(self):
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pin = self.inv_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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for pin_name in ["A", "B", "C"]:
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pin = self.nand_inst.get_pin(pin_name)
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self.add_layout_pin_rect_center(text=pin_name,
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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def analytical_delay(self, corner, slew, load=0.0):
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""" Calculate the analytical delay of DFF-> INV -> INV """
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nand_delay = self.nand.analytical_delay(corner,
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slew=slew,
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load=self.inv.input_load())
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inv_delay = self.inv.analytical_delay(corner,
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slew=nand_delay.slew,
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load=load)
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return nand_delay + inv_delay
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def get_stage_efforts(self, external_cout, inp_is_rise=False):
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"""Get the stage efforts of the A or B -> Z path"""
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stage_effort_list = []
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stage1_cout = self.inv.get_cin()
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stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise)
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stage_effort_list.append(stage1)
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last_stage_is_rise = stage1.is_rise
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stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise)
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stage_effort_list.append(stage2)
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return stage_effort_list
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def get_cin(self):
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"""Return the relative input capacitance of a single input"""
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return self.nand.get_cin()
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@@ -0,0 +1,159 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
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# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
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import debug
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from vector import vector
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import design
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from sram_factory import factory
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from globals import OPTS
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from tech import layer
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class and4_dec(design.design):
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"""
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This is an AND with configurable drive strength.
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"""
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def __init__(self, name, size=1, height=None, add_wells=True):
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design.design.__init__(self, name)
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debug.info(1, "Creating and4_dec {}".format(name))
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self.add_comment("size: {}".format(size))
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self.size = size
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self.height = height
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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self.nand = factory.create(module_type="nand4_dec",
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height=self.height)
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self.inv = factory.create(module_type="inv_dec",
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height=self.height,
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size=self.size)
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self.add_mod(self.nand)
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self.add_mod(self.inv)
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def create_layout(self):
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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self.width = self.nand.width + self.inv.width
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self.height = self.nand.height
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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self.route_supply_rails()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin("A", "INPUT")
|
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self.add_pin("B", "INPUT")
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self.add_pin("C", "INPUT")
|
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self.add_pin("D", "INPUT")
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self.add_pin("Z", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_insts(self):
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self.nand_inst = self.add_inst(name="pand4_dec_nand",
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mod=self.nand)
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self.connect_inst(["A", "B", "C", "D", "zb_int", "vdd", "gnd"])
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self.inv_inst = self.add_inst(name="pand4_dec_inv",
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mod=self.inv)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
|
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# Add NAND to the right
|
||||
self.nand_inst.place(offset=vector(0, 0))
|
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|
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# Add INV to the right
|
||||
self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0))
|
||||
|
||||
def route_supply_rails(self):
|
||||
""" Add vdd/gnd rails to the top, (middle), and bottom. """
|
||||
if OPTS.tech_name == "sky130":
|
||||
for name in ["vdd", "gnd"]:
|
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for inst in [self.nand_inst, self.inv_inst]:
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self.copy_layout_pin(inst, name)
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else:
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self.add_layout_pin_rect_center(text="gnd",
|
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layer=self.route_layer,
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offset=vector(0.5 * self.width, 0),
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width=self.width)
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self.add_layout_pin_rect_center(text="vdd",
|
||||
layer=self.route_layer,
|
||||
offset=vector(0.5 * self.width, self.height),
|
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width=self.width)
|
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||||
def add_wires(self):
|
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# nand Z to inv A
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z1_pin = self.nand_inst.get_pin("Z")
|
||||
a2_pin = self.inv_inst.get_pin("A")
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||||
if OPTS.tech_name == "sky130":
|
||||
mid1_point = vector(a2_pin.cx(), z1_pin.cy())
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else:
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mid1_point = vector(z1_pin.cx(), a2_pin.cy())
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||||
self.add_path(self.route_layer,
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[z1_pin.center(), mid1_point, a2_pin.center()])
|
||||
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def add_layout_pins(self):
|
||||
pin = self.inv_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
for pin_name in ["A", "B", "C", "D"]:
|
||||
pin = self.nand_inst.get_pin(pin_name)
|
||||
self.add_layout_pin_rect_center(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
def analytical_delay(self, corner, slew, load=0.0):
|
||||
""" Calculate the analytical delay of DFF-> INV -> INV """
|
||||
nand_delay = self.nand.analytical_delay(corner,
|
||||
slew=slew,
|
||||
load=self.inv.input_load())
|
||||
inv_delay = self.inv.analytical_delay(corner,
|
||||
slew=nand_delay.slew,
|
||||
load=load)
|
||||
return nand_delay + inv_delay
|
||||
|
||||
def get_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
"""Get the stage efforts of the A or B -> Z path"""
|
||||
stage_effort_list = []
|
||||
stage1_cout = self.inv.get_cin()
|
||||
stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
last_stage_is_rise = stage1.is_rise
|
||||
|
||||
stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise)
|
||||
stage_effort_list.append(stage2)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_cin(self):
|
||||
"""Return the relative input capacitance of a single input"""
|
||||
return self.nand.get_cin()
|
||||
|
||||
@@ -1,97 +0,0 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import design
|
||||
import debug
|
||||
import utils
|
||||
from tech import GDS, layer, parameter, drc
|
||||
from tech import cell_properties as props
|
||||
import logical_effort
|
||||
|
||||
|
||||
class sense_amp(design.design):
|
||||
"""
|
||||
This module implements the single sense amp cell used in the design. It
|
||||
is a hand-made cell, so the layout and netlist should be available in
|
||||
the technology library.
|
||||
Sense amplifier to read a pair of bit-lines.
|
||||
"""
|
||||
pin_names = [props.sense_amp.pin.bl,
|
||||
props.sense_amp.pin.br,
|
||||
props.sense_amp.pin.dout,
|
||||
props.sense_amp.pin.en,
|
||||
props.sense_amp.pin.vdd,
|
||||
props.sense_amp.pin.gnd]
|
||||
type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
|
||||
cell_size_layer = "boundary"
|
||||
|
||||
def __init__(self, name="sense_amp"):
|
||||
super().__init__(name)
|
||||
debug.info(2, "Create sense_amp")
|
||||
|
||||
(width, height) = utils.get_libcell_size(name,
|
||||
GDS["unit"],
|
||||
layer[self.cell_size_layer])
|
||||
|
||||
pin_map = utils.get_libcell_pins(self.pin_names,
|
||||
name,
|
||||
GDS["unit"])
|
||||
|
||||
self.width = width
|
||||
self.height = height
|
||||
self.pin_map = pin_map
|
||||
self.add_pin_types(self.type_list)
|
||||
|
||||
def get_bl_names(self):
|
||||
return props.sense_amp.pin.bl
|
||||
|
||||
def get_br_names(self):
|
||||
return props.sense_amp.pin.br
|
||||
|
||||
@property
|
||||
def dout_name(self):
|
||||
return props.sense_amp.pin.dout
|
||||
|
||||
@property
|
||||
def en_name(self):
|
||||
return props.sense_amp.pin.en
|
||||
|
||||
def get_cin(self):
|
||||
|
||||
# FIXME: This input load will be applied to both the s_en timing and bitline timing.
|
||||
|
||||
# Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
|
||||
from tech import spice
|
||||
# Default is 8x. Per Samira and Hodges-Jackson book:
|
||||
# "Column-mux transistors driven by the decoder must be sized for optimal speed"
|
||||
bitline_pmos_size = 8 # FIXME: This should be set somewhere and referenced. Probably in tech file.
|
||||
return spice["min_tx_drain_c"] * bitline_pmos_size # ff
|
||||
|
||||
def get_stage_effort(self, load):
|
||||
# Delay of the sense amp will depend on the size of the amp and the output load.
|
||||
parasitic_delay = 1
|
||||
cin = (parameter["sa_inv_pmos_size"] + parameter["sa_inv_nmos_size"]) / drc("minwidth_tx")
|
||||
sa_size = parameter["sa_inv_nmos_size"] / drc("minwidth_tx")
|
||||
cc_inv_cin = cin
|
||||
return logical_effort.logical_effort('column_mux', sa_size, cin, load + cc_inv_cin, parasitic_delay, False)
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Returns dynamic and leakage power. Results in nW"""
|
||||
# Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
|
||||
total_power = self.return_power()
|
||||
return total_power
|
||||
|
||||
def get_enable_name(self):
|
||||
"""Returns name used for enable net"""
|
||||
# FIXME: A better programmatic solution to designate pins
|
||||
enable_name = self.en_name
|
||||
debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name))
|
||||
return enable_name
|
||||
|
||||
def build_graph(self, graph, inst_name, port_nets):
|
||||
"""Adds edges based on inputs/outputs. Overrides base class function."""
|
||||
self.add_graph_edges(graph, port_nets)
|
||||
Reference in New Issue
Block a user