Added some power functions.

compiler/modules/bank.py

@@ -1232,6 +1232,7 @@ class bank(design.design):
     def analytical_power(self, slew, load):
         """ return  analytical power of the bank. Basic skeleton code"""
         msf_addr_power = self.msf_address.analytical_power(slew, self.decoder.input_load())
+        msf_data_in_power = self.msf_data_in.analytical_power(slew, self.decoder.input_load())
         
         decoder_power = self.decoder.analytical_power(slew, load)
         
@@ -1244,6 +1245,6 @@ class bank(design.design):
         
         data_t_DATA_power = self.tri_gate_array.analytical_power(slew, load)
         
-        total_power = msf_addr_power + decoder_power + word_driver_power \
+        total_power = msf_addr_power + msf_data_in_power + decoder_power + word_driver_power \
                       + bitcell_array_power + bl_t_data_out_power + data_t_DATA_power
         return total_power

compiler/modules/bitcell.py

@@ -37,5 +37,8 @@ class bitcell(design.design):
         
     def analytical_power(self, slew, load=0, swing = 0.5):
         #Power of the bitcell. Mostly known for leakage, but dynamic can also be factored in.
-        #Just skeleton code for now which returns a magic number.
-        return 5
+        #Only consider leakage power for now. Value defined in tech file rather than calculated.
+        from tech import spice
+        leakage = spice["bitcell_leakage"]
+        total_power = leakage
+        return total_power

compiler/modules/bitcell_array.py

@@ -196,8 +196,8 @@ class bitcell_array(design.design):
         #Calculate the bitcell power which can include leakage as well as bitline dynamic
         cell_power = self.cell.analytical_power(slew, cell_load, swing = bl_swing)
 
-        #we do not consider the delay over the wire for now
-        return cell_power
+        #calculate power for entire array based off a single cell
+        return cell_power * self.column_size * self.row_size
 
     def gen_wl_wire(self):
         wl_wire = self.generate_rc_net(int(self.column_size), self.width, drc["minwidth_metal1"])

compiler/modules/control_logic.py

@@ -688,3 +688,8 @@ class control_logic(design.design):
                            width=pin.width())
         
         
+    def analytical_power(self, slew, load):
+        #This has yet to be fully determined. 
+        msf_power = self.msf_control.analytical_power(slew, load)
+        #currently, only return flop array power
+        return msf_power

compiler/modules/ms_flop.py

@@ -28,5 +28,7 @@ class ms_flop(design.design):
         return result
         
     def analytical_power(self, slew, load = 0.0):
-        return 4
+        #Value taken from tech file.
+        from tech import spice
+        return spice["msflop_power"]
 

compiler/modules/ms_flop_array.py

@@ -136,4 +136,4 @@ class ms_flop_array(design.design):
         return self.ms.analytical_delay(slew=slew, load=load)
         
     def analytical_power(self, slew, load):
-        return self.ms.analytical_power(slew=slew, load=load)
+        return self.columns * self.ms.analytical_power(slew=slew, load=load)