mirror of https://github.com/VLSIDA/OpenRAM.git
fix end subckt typo
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@ -11,5 +11,5 @@ MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n
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* Access transistors
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* Access transistors
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MM3 bl_noconn wl Q gnd NMOS_VTG W=135.00n L=50n
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MM3 bl_noconn wl Q gnd NMOS_VTG W=135.00n L=50n
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MM2 br_noconn wl Q_bar gnd NMOS_VTG W=135.00n L=50n
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MM2 br_noconn wl Q_bar gnd NMOS_VTG W=135.00n L=50n
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.ENDS cell_1rw
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.ENDS dummy_cell_1rw
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