update test/module imports related to delay control

compiler/modules/control_logic_delay.py

@@ -5,13 +5,15 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
+
-import debug
-from sram_factory import factory
 import math
-from base import vector
+from openram import debug
-from globals import OPTS
+from openram import OPTS
-from base import logical_effort
+from openram.base import design
+from openram.base import vector
+from openram.base import logical_effort
+from openram.sram_factory import factory
+from .control_logic_base import control_logic_base
 
 
 class control_logic_delay(design):

compiler/modules/multi_delay_chain.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
-from base import design
+from openram.base import design
-from base import vector
+from openram.base import vector
-from globals import OPTS
+from openram.sram_factory import factory
-from sram_factory import factory
+from openram import OPTS
 
 
 class multi_delay_chain(design):

compiler/tests/16_control_logic_delay_multiport_test.py

@@ -10,20 +10,21 @@
 Run a regression test on a control_logic_delay
 """
 
-import unittest
-from testutils import header,openram_test
 import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
 
 class control_logic_delay_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check control logic for multi-port
         OPTS.bitcell = "pbitcell"
@@ -48,11 +49,11 @@ class control_logic_delay_test(openram_test):
         a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="r")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main()

compiler/tests/16_control_logic_delay_r_test.py

@@ -6,31 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
+import openram
-from globals import OPTS
+from openram import debug
-from sram_factory import factory
+from openram.sram_factory import factory
-import debug
+from openram import OPTS
 
 
 class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for control_logic_r")
         a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32, port_type="r")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())

compiler/tests/16_control_logic_delay_rw_test.py

@@ -6,31 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
+import openram
-from globals import OPTS
+from openram import debug
-from sram_factory import factory
+from openram.sram_factory import factory
-import debug
+from openram import OPTS
 
 
 class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for control_logic_rw")
         a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())

compiler/tests/16_control_logic_delay_w_test.py

@@ -6,30 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
+import openram
-from globals import OPTS
+from openram import debug
-from sram_factory import factory
+from openram.sram_factory import factory
-import debug
+from openram import OPTS
+
 
 class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for control_logic_w")
         a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32, port_type="w")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())