mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 cleanup
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43fe1ae023
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@ -9,6 +9,7 @@ import debug
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from drc_value import *
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from drc_value import *
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from drc_lut import *
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from drc_lut import *
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class design_rules(dict):
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class design_rules(dict):
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"""
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"""
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This is a class that implements the design rules structures.
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This is a class that implements the design rules structures.
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@ -7,6 +7,7 @@
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#
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#
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import debug
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import debug
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class drc_lut():
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class drc_lut():
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"""
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"""
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Implement a lookup table of rules.
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Implement a lookup table of rules.
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@ -32,15 +33,14 @@ class drc_lut():
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if self.match(key, table_key):
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if self.match(key, table_key):
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return self.table[table_key]
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return self.table[table_key]
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def match(self, key1, key2):
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def match(self, key1, key2):
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"""
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"""
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Determine if key1>=key2 for all tuple pairs.
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Determine if key1>=key2 for all tuple pairs.
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(i.e. return false if key1<key2 for any pair.)
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(i.e. return false if key1<key2 for any pair.)
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"""
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"""
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# If any one pair is less than, return False
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# If any one pair is less than, return False
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debug.check(len(key1)==len(key2),"Comparing invalid key lengths.")
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debug.check(len(key1) == len(key2), "Comparing invalid key lengths.")
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for k1,k2 in zip(key1,key2):
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for k1, k2 in zip(key1, key2):
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if k1 < k2:
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if k1 < k2:
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return False
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return False
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return True
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return True
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@ -6,6 +6,7 @@
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# All rights reserved.
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# All rights reserved.
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#
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#
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class drc_value():
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class drc_value():
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"""
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"""
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A single DRC value.
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A single DRC value.
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