Merge branch 'dev' into davideschiavone-patch-1

README.md

@@ -53,6 +53,7 @@ You must set two environment variables:
 + OPENRAM\_HOME should point to the compiler source directory.
 + OPENERAM\_TECH should point to one or more root technology directories (colon separated).
 
+You should also add OPENRAM\_HOME to your PYTHONPATH.
 
 For example add this to your .bashrc:
 
@@ -62,10 +63,10 @@ For example add this to your .bashrc:
 ```
 
 You should also add OPENRAM\_HOME to your PYTHONPATH:
-
 ```
   export PYTHONPATH=$OPENRAM_HOME
 ```
+
 Note that if you want symbols to resolve in your editor, you may also want to add the specific technology
 directory that you use and any custom technology modules as well. For example:
 ```

compiler/base/lef.py

@@ -220,4 +220,3 @@ class lef:
                                                  round(item[1],
                                                        self.round_grid)))
             self.lef.write(" ;\n")
-

compiler/base/timing_graph.py

@@ -153,4 +153,3 @@ class timing_graph():
         """ override print function output """
 
         return str(self)
-

compiler/characterizer/cacti.py

@@ -118,5 +118,3 @@ class cacti(simulation):
         debug.info(1, "Dynamic Power: {0} mW".format(power.dynamic))
         debug.info(1, "Leakage Power: {0} mW".format(power.leakage))
         return power
-        
-    

compiler/characterizer/linear_regression.py

@@ -40,4 +40,3 @@ class linear_regression(regression_model):
 
         pred = model.predict(features)
         return pred
-        

compiler/characterizer/measurements.py

@@ -211,4 +211,3 @@ class voltage_at_measure(spice_measurement):
             meas_name = self.name
             targ_name = self.targ_name_no_port
         return (meas_name, targ_name, time_at)
-

compiler/characterizer/model_check.py

@@ -448,6 +448,3 @@ class model_check(delay):
             name_dict[self.sae_model_name] = name_dict["sae_measures"]
 
         return name_dict
-
-
-

compiler/characterizer/neural_network.py

@@ -41,4 +41,3 @@ class neural_network(regression_model):
         pred = model.predict(features)
         reshape_pred = np.reshape(pred, (len(pred),1))
         return reshape_pred
-        

compiler/characterizer/regression_model.py

@@ -205,4 +205,3 @@ class regression_model(simulation):
         OPTS.model_dict[model_name+"_coef"] = list(model.coef_[0])
         debug.info(1,"Coefs of {}:{}".format(model_name,OPTS.model_dict[model_name+"_coef"]))
         OPTS.model_dict[model_name+"_intercept"] = float(model.intercept_)
-        

compiler/debug.py

@@ -134,4 +134,3 @@ def bp():
     and whenever you encounter the debug.bp() they won't be "reset".
     """
     pass
-        

compiler/drc/custom_cell_properties.py

@@ -290,4 +290,3 @@ class cell_properties():
     @property
     def row_cap_2port(self):
         return self._row_cap_2port
-    

compiler/model_data_util.py

@@ -267,27 +267,3 @@ if __name__ == "__main__":
         input_dir_path = sys.argv[1]
         out_path = sys.argv[2]
         gen_model_csv(input_dir_path, out_path)
-
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compiler/modules/replica_bitcell_array.py

@@ -309,8 +309,8 @@ class replica_bitcell_array(bitcell_base_array):
 
         # This creates space for the unused wordline connections as well as the
         # row-based or column based power and ground lines.
-        self.vertical_pitch = getattr(self, "{}_pitch".format(self.supply_stack[0]))
+        self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0]))
-        self.horizontal_pitch = getattr(self, "{}_pitch".format(self.supply_stack[2]))
+        self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2]))
         self.unused_offset = vector(0.25, 0.25)
 
         # This is a bitcell x bitcell offset to scale
@@ -495,16 +495,7 @@ class replica_bitcell_array(bitcell_base_array):
         else:
             bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
 
-        wl_layer = bitcell.wl_layer
-        wl_dir = bitcell.wl_dir
-
-        bl_layer = bitcell.bl_layer
-        bl_dir = bitcell.bl_dir
-
-        vdd_layer = bitcell.vdd_layer
         vdd_dir = bitcell.vdd_dir
-
-        gnd_layer = bitcell.gnd_layer
         gnd_dir = bitcell.gnd_dir
 
         # vdd/gnd are only connected in the perimeter cells
@@ -514,8 +505,6 @@ class replica_bitcell_array(bitcell_base_array):
         top_bot_mult = 1
         left_right_mult = 1
 
-        vdd_locs = []
-        gnd_locs = []
         # There are always vertical pins for the WLs on the left/right if we have unused wordlines
         self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult)
         self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult)

compiler/router/grid.py

@@ -213,8 +213,3 @@ class grid:
         """
         path.set_path(False)
         path.set_blocked(True)
-
-
-
-
-

compiler/router/grid_cell.py

@@ -49,4 +49,3 @@ class grid_cell:
             type_string += "P"
 
         return type_string
-

compiler/router/signal_escape_router.py

@@ -102,5 +102,3 @@ class signal_escape_router(router):
             #     breakpoint()
 
         self.write_debug_gds("debug_route.gds", True)
-
-

compiler/router/supply_grid.py

@@ -77,5 +77,3 @@ class supply_grid(signal_grid):
             wave = wave_path.neighbor(direct)
 
         return wave_path
-
-

compiler/router/supply_grid_router.py

@@ -392,4 +392,3 @@ class supply_grid_router(router):
         debug.info(4, "Blocking supply rail")
         for rail_name in self.supply_rail_tracks:
             self.rg.set_blocked(self.supply_rail_tracks[rail_name])
-

compiler/tests/00_code_format_check_test.py

@@ -28,6 +28,7 @@ class code_format_test(openram_test):
                 continue
             errors += check_file_format_tab(code)
             errors += check_file_format_carriage(code)
+            errors += check_file_format_whitespace(code)
 
         for code in source_codes:
             if re.search("gdsMill", code):
@@ -51,7 +52,7 @@ def setup_files(path):
     files = []
     for (dir, _, current_files) in os.walk(path):
         for f in current_files:
-            files.append(os.getenv("OPENRAM_HOME"))
+            files.append(os.path.join(dir, f))
     nametest = re.compile("\.py$", re.IGNORECASE)
     select_files = list(filter(nametest.search, files))
     return select_files
@@ -92,13 +93,35 @@ def check_file_format_carriage(file_name):
         if len(key_positions)>10:
             line_numbers = key_positions[:10] + [" ..."]
         else:
-            line_numbers = key_positoins
+            line_numbers = key_positions
         debug.info(0, '\nFound ' + str(len(key_positions)) + ' carriage returns in ' +
                    str(file_name) + ' (lines ' + ",".join(str(x) for x in line_numbers) + ')')
     f.close()
     return len(key_positions)
 
 
+def check_file_format_whitespace(file_name):
+    """
+    Check if file contains a line with whitespace at the end
+    and return the number of these lines.
+    """
+
+    f = open(file_name, "r")
+    key_positions = []
+    for num, line in enumerate(f.readlines()):
+        if re.match(r".*[ \t]$", line):
+            key_positions.append(num)
+    if len(key_positions) > 0:
+        if len(key_positions) > 10:
+            line_numbers = key_positions[:10] + [" ..."]
+        else:
+            line_numbers = key_positions
+        debug.info(0, "\nFound " + str(len(key_positions)) + " ending whitespace in " +
+                   str(file_name) + " (lines " + ",".join(str(x) for x in line_numbers) + ")")
+    f.close()
+    return len(key_positions)
+
+
 def check_print_output(file_name):
     """Check if any files (except debug.py) call the _print_ function. We should
     use the debug output with verbosity instead!"""

setpaths.sh

@@ -7,9 +7,3 @@
 export OPENRAM_HOME="`pwd`/compiler"
 export OPENRAM_TECH="`pwd`/technology"
 export PYTHONPATH=$OPENRAM_HOME
-for dir in `pwd`/compiler/*
-do
-	if [ -d $dir ]; then 
-		export PYTHONPATH=$PYTHONPATH:$dir
-	fi;
-done