mirror of https://github.com/VLSIDA/OpenRAM.git
Remove 4 bank code and test for now.
This commit is contained in:
Matt Guthaus
parent
7054d0881a
commit
14fa33e21d
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@ -34,8 +34,6 @@ class sram():
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from sram_1bank import sram_1bank as sram
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from sram_1bank import sram_1bank as sram
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elif self.num_banks == 2:
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elif self.num_banks == 2:
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from sram_2bank import sram_2bank as sram
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from sram_2bank import sram_2bank as sram
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elif self.num_banks == 4:
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from sram_4bank import sram_4bank as sram
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else:
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else:
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debug.error("Invalid number of banks.",-1)
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debug.error("Invalid number of banks.",-1)
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@ -1,331 +0,0 @@
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import sys
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from tech import drc, spice
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import debug
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from math import log,sqrt,ceil
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import datetime
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import getpass
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from vector import vector
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from globals import OPTS, print_time
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from sram_base import sram_base
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from bank import bank
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from dff_buf_array import dff_buf_array
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from dff_array import dff_array
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class sram_4bank(sram_base):
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"""
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Procedures specific to a four bank SRAM.
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"""
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def __init__(self, name, sram_config):
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sram_base.__init__(self, name, sram_config)
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def compute_bank_offsets(self):
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""" Compute the overall offsets for a four bank SRAM """
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# The main difference is that the four bank SRAM has the data bus in the middle of the four banks
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# as opposed to the top of the banks.
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# In 4 bank SRAM, the height is determined by the bank decoder and address flop
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self.vertical_bus_height = 2*self.bank.height + 4*self.bank_to_bus_distance + self.data_bus_height \
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+ self.supply_bus_height + self.msb_decoder.height + self.msb_address.width
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# The address bus extends down through the power rails, but control and bank_sel bus don't
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self.addr_bus_height = self.vertical_bus_height
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self.vertical_bus_offset = vector(self.bank.width + self.bank_to_bus_distance, 0)
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self.data_bus_offset = vector(0, self.bank.height + self.bank_to_bus_distance)
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self.supply_bus_offset = vector(0, self.data_bus_offset.y + self.data_bus_height \
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+ self.bank.height + 2*self.bank_to_bus_distance)
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self.control_bus_offset = vector(0, self.supply_bus_offset.y + self.supply_bus_height)
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self.bank_sel_bus_offset = self.vertical_bus_offset + vector(self.m2_pitch*self.control_size,0)
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self.addr_bus_offset = self.bank_sel_bus_offset.scale(1,0) + vector(self.m2_pitch*self.num_banks,0)
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# Control is placed at the top above the control bus and everything
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self.control_logic_position = vector(0, self.control_bus_offset.y + self.control_bus_height + self.m1_pitch)
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# Bank select flops get put to the right of control logic above bank1 and the buses
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# Leave a pitch to get the vdd rails up to M2
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self.msb_address_position = vector(self.bank_inst[1].lx() + 3*self.supply_rail_pitch,
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self.supply_bus_offset.y + self.supply_bus_height \
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+ 2*self.m1_pitch + self.msb_address.width)
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# Decoder goes above the MSB address flops, and is flipped in Y
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# separate the two by a bank to bus distance for nwell rules, just in case
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self.msb_decoder_position = self.msb_address_position + vector(self.msb_decoder.width, self.bank_to_bus_distance)
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def add_modules(self):
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""" Adds the modules and the buses to the top level """
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self.compute_bus_sizes()
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self.add_banks()
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self.compute_bank_offsets()
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self.add_busses()
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self.add_logic()
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self.width = self.bank_inst[1].ur().x
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self.height = max(self.control_logic_inst.uy(),self.msb_decoder_inst.uy())
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def add_banks(self):
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# Placement of bank 0 (upper left)
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bank_position_0 = vector(self.bank.width,
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self.bank.height + self.data_bus_height + 2*self.bank_to_bus_distance)
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self.bank_inst=[self.add_bank(0, bank_position_0, 1, -1)]
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# Placement of bank 1 (upper right)
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x_off = self.bank.width + self.vertical_bus_width + 2*self.bank_to_bus_distance
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bank_position_1 = vector(x_off, bank_position_0.y)
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self.bank_inst.append(self.add_bank(1, bank_position_1, 1, 1))
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# Placement of bank 2 (bottom left)
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y_off = self.bank.height
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bank_position_2 = vector(bank_position_0.x, y_off)
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self.bank_inst.append(self.add_bank(2, bank_position_2, -1, -1))
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# Placement of bank 3 (bottom right)
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bank_position_3 = vector(bank_position_1.x, bank_position_2.y)
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self.bank_inst.append(self.add_bank(3, bank_position_3, -1, 1))
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def add_logic(self):
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""" Add the control and MSB decode/bank select logic for four banks """
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self.add_control_logic(position=self.control_logic_position)
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self.msb_address_inst = self.add_inst(name="msb_address",
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mod=self.msb_address,
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offset=self.msb_address_position,
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rotate=270)
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self.msb_bank_sel_addr = ["ADDR[{}]".format(i) for i in range(self.addr_size-2,self.addr_size,1)]
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temp = list(self.msb_bank_sel_addr)
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temp.extend(["msb{0}[{1}]".format(j,i) for i in range(2) for j in ["","_bar"]])
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temp.extend(["clk_buf", "vdd", "gnd"])
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self.connect_inst(temp)
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self.msb_decoder_inst = self.add_inst(name="msb_decoder",
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mod=self.msb_decoder,
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offset=self.msb_decoder_position,
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mirror="MY")
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temp = ["msb[{}]".format(i) for i in range(2)]
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temp.extend(["bank_sel[{}]".format(i) for i in range(4)])
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def route_double_msb_address(self):
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""" Route two MSB address bits and the bank decoder for 4-bank SRAM """
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# connect the MSB flops to the address input bus
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for i in [0,1]:
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msb_pins = self.msb_address_inst.get_pins("din_{}".format(i))
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for msb_pin in msb_pins:
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if msb_pin.layer == "metal3":
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msb_pin_pos = msb_pin.lc()
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break
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rail_pos = vector(self.vert_control_bus_positions[self.msb_bank_sel_addr[i]].x,msb_pin_pos.y)
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self.add_path("metal3",[msb_pin_pos,rail_pos])
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self.add_via_center(("metal2","via2","metal3"),rail_pos)
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# Connect clk
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clk_pin = self.msb_address_inst.get_pin("clk")
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clk_pos = clk_pin.bc()
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rail_pos = self.horz_control_bus_positions["clk_buf"]
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bend_pos = vector(clk_pos.x,self.horz_control_bus_positions["clk_buf"].y)
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self.add_path("metal1",[clk_pos,bend_pos,rail_pos])
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# Connect bank decoder outputs to the bank select vertical bus wires
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for i in range(self.num_banks):
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msb_pin = self.msb_decoder_inst.get_pin("out_{}".format(i))
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msb_pin_pos = msb_pin.lc()
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rail_pos = vector(self.vert_control_bus_positions["bank_sel[{}]".format(i)].x,msb_pin_pos.y)
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self.add_path("metal1",[msb_pin_pos,rail_pos])
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self.add_via_center(("metal1","via1","metal2"),rail_pos)
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# connect MSB flop outputs to the bank decoder inputs
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msb_pin = self.msb_address_inst.get_pin("dout[0]")
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msb_pin_pos = msb_pin.rc()
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in_pin = self.msb_decoder_inst.get_pin("in[0]")
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in_pos = in_pin.bc() + vector(0,1*self.m2_pitch,) # pin is up from bottom
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out_pos = msb_pin_pos + vector(1*self.m2_pitch,0) # route out to the right
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up_pos = vector(out_pos.x,in_pos.y) # and route up to the decoer
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self.add_wire(("metal1","via1","metal2"),[msb_pin_pos,out_pos,up_pos,in_pos])
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self.add_via_center(("metal1","via1","metal2"),in_pos)
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self.add_via_center(("metal1","via1","metal2"),msb_pin_pos,rotate=90)
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msb_pin = self.msb_address_inst.get_pin("dout[1]")
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msb_pin_pos = msb_pin.rc()
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in_pin = self.msb_decoder_inst.get_pin("in[1]")
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in_pos = in_pin.bc() + vector(0,self.bitcell.height+self.m2_pitch) # route the next row up
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out_pos = msb_pin_pos + vector(2*self.m2_pitch,0) # route out to the right
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up_pos = vector(out_pos.x,in_pos.y) # and route up to the decoer
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self.add_wire(("metal1","via1","metal2"),[msb_pin_pos,out_pos,up_pos,in_pos])
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self.add_via_center(("metal1","via1","metal2"),in_pos)
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self.add_via_center(("metal1","via1","metal2"),msb_pin_pos,rotate=90)
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self.route_double_msb_address_supplies()
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def route_double_msb_address_supplies(self):
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""" Route the vdd/gnd bits of the 2-bit bank decoder. """
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# Route the right-most vdd/gnd of the right upper bank to the top of the decoder
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vdd_pins = self.bank_inst[1].get_pins("vdd")
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left_bank_vdd_pin = None
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right_bank_vdd_pin = None
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for vdd_pin in vdd_pins:
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if vdd_pin.layer != "metal2":
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continue
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if left_bank_vdd_pin == None or vdd_pin.lx()<left_bank_vdd_pin.lx():
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left_bank_vdd_pin = vdd_pin
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if right_bank_vdd_pin == None or vdd_pin.lx()>right_bank_vdd_pin.lx():
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right_bank_vdd_pin = vdd_pin
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# Route to top
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self.add_rect(layer="metal2",
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offset=vdd_pin.ul(),
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height=self.height-vdd_pin.uy(),
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width=vdd_pin.width())
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gnd_pins = self.bank_inst[1].get_pins("gnd")
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left_bank_gnd_pin = None
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right_bank_gnd_pin = None
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for gnd_pin in gnd_pins:
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if gnd_pin.layer != "metal2":
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continue
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if left_bank_gnd_pin == None or gnd_pin.lx()<left_bank_gnd_pin.lx():
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left_bank_gnd_pin = gnd_pin
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if right_bank_gnd_pin == None or gnd_pin.lx()>right_bank_gnd_pin.lx():
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right_bank_gnd_pin = gnd_pin
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# Route to top
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self.add_rect(layer="metal2",
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offset=gnd_pin.ul(),
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height=self.height-gnd_pin.uy(),
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width=gnd_pin.width())
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# Connect bank decoder vdd/gnd supplies using the previous bank pins
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vdd_pins = self.msb_decoder_inst.get_pins("vdd")
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for vdd_pin in vdd_pins:
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if vdd_pin.layer != "metal1":
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continue
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rail1_pos = vector(left_bank_vdd_pin.cx(),vdd_pin.cy())
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rail2_pos = vector(right_bank_vdd_pin.cx(),vdd_pin.cy())
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self.add_path("metal1",[rail1_pos,rail2_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=rail1_pos,
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rotate=90,
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size=[1,3])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=rail2_pos,
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rotate=90,
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size=[1,3])
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gnd_pins = self.msb_decoder_inst.get_pins("gnd")
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for gnd_pin in gnd_pins:
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if gnd_pin.layer != "metal1":
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continue
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rail1_pos = vector(left_bank_gnd_pin.cx(),gnd_pin.cy())
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rail2_pos = vector(right_bank_gnd_pin.cx(),gnd_pin.cy())
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self.add_path("metal1",[rail1_pos,rail2_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=rail1_pos,
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rotate=90,
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size=[1,3])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=rail2_pos,
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rotate=90,
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size=[1,3])
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# connect the bank MSB flop supplies
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vdd_pins = self.msb_address_inst.get_pins("vdd")
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# vdd pins go down to the rail
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for vdd_pin in vdd_pins:
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if vdd_pin.layer != "metal1":
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continue
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vdd_pos = vdd_pin.bc()
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down_pos = vdd_pos - vector(0,self.m1_pitch)
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rail_pos = vector(vdd_pos.x,self.horz_control_bus_positions["vdd"].y)
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self.add_path("metal1",[vdd_pos,down_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=down_pos,
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rotate=90)
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self.add_path("metal2",[down_pos,rail_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=rail_pos)
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# gnd pins go right to the rail
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gnd_pins = self.msb_address_inst.get_pins("gnd")
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for gnd_pin in gnd_pins:
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if gnd_pin.layer != "metal2":
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continue
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rail1_pos = vector(left_bank_gnd_pin.cx(),gnd_pin.cy())
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self.add_path("metal1",[rail1_pos,gnd_pin.lc()])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=gnd_pin.lc(),
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rotate=90)
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=rail1_pos,
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rotate=90,
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size=[1,3])
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def route(self):
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""" Route all of the signals for the four bank SRAM. """
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self.route_shared_banks()
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# connect the data output to the data bus
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for n in self.data_bus_names:
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for i in [0,1]:
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pin_pos = self.bank_inst[i].get_pin(n).bc()
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rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y)
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self.add_path("metal2",[pin_pos,rail_pos])
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self.add_via_center(("metal2","via2","metal3"),rail_pos)
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for i in [2,3]:
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pin_pos = self.bank_inst[i].get_pin(n).uc()
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rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y)
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self.add_path("metal2",[pin_pos,rail_pos])
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self.add_via_center(("metal2","via2","metal3"),rail_pos)
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# route msb address bits
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# route 2:4 decoder
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self.route_double_msb_address()
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# connect the banks to the vertical address bus
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# connect the banks to the vertical control bus
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for n in self.addr_bus_names + self.control_bus_names:
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# Skip these from the horizontal bus
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if n in ["vdd", "gnd"]: continue
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# This will be the bank select, so skip it
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if n in self.msb_bank_sel_addr: continue
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for bank_id in [0,2]:
|
|
||||||
pin0_pos = self.bank_inst[bank_id].get_pin(n).rc()
|
|
||||||
pin1_pos = self.bank_inst[bank_id+1].get_pin(n).lc()
|
|
||||||
rail_pos = vector(self.vert_control_bus_positions[n].x,pin0_pos.y)
|
|
||||||
self.add_path("metal3",[pin0_pos,pin1_pos])
|
|
||||||
self.add_via_center(("metal2","via2","metal3"),rail_pos)
|
|
||||||
|
|
||||||
|
|
||||||
self.route_bank_supply_rails(left_banks=[0,2], bottom_banks=[2,3])
|
|
||||||
|
|
||||||
|
|
||||||
def add_lvs_correspondence_points(self):
|
|
||||||
"""
|
|
||||||
This adds some points for easier debugging if LVS goes wrong.
|
|
||||||
These should probably be turned off by default though, since extraction
|
|
||||||
will show these as ports in the extracted netlist.
|
|
||||||
"""
|
|
||||||
|
|
||||||
if self.num_banks==1: return
|
|
||||||
|
|
||||||
for n in self.control_bus_names:
|
|
||||||
self.add_label(text=n,
|
|
||||||
layer="metal2",
|
|
||||||
offset=self.vert_control_bus_positions[n])
|
|
||||||
for n in self.bank_sel_bus_names:
|
|
||||||
self.add_label(text=n,
|
|
||||||
layer="metal2",
|
|
||||||
offset=self.vert_control_bus_positions[n])
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
#!/usr/bin/env python3
|
|
||||||
"""
|
|
||||||
Run a regression test on a 4 bank SRAM
|
|
||||||
"""
|
|
||||||
|
|
||||||
import unittest
|
|
||||||
from testutils import header,openram_test
|
|
||||||
import sys,os
|
|
||||||
sys.path.append(os.path.join(sys.path[0],".."))
|
|
||||||
import globals
|
|
||||||
from globals import OPTS
|
|
||||||
import debug
|
|
||||||
|
|
||||||
@unittest.skip("Multibank is not working yet.")
|
|
||||||
class sram_4bank_test(openram_test):
|
|
||||||
|
|
||||||
def runTest(self):
|
|
||||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
|
||||||
from sram import sram
|
|
||||||
from sram_config import sram_config
|
|
||||||
c = sram_config(word_size=16,
|
|
||||||
num_words=64,
|
|
||||||
num_banks=4)
|
|
||||||
|
|
||||||
debug.info(1, "Four bank, no column mux with control logic")
|
|
||||||
a = sram(c, "sram1")
|
|
||||||
self.local_check(a, final_verification=True)
|
|
||||||
|
|
||||||
c.num_words=128
|
|
||||||
c.words_per_row=2
|
|
||||||
debug.info(1, "Four bank two way column mux with control logic")
|
|
||||||
a = sram(c, "sram2")
|
|
||||||
self.local_check(a, final_verification=True)
|
|
||||||
|
|
||||||
c.num_words=256
|
|
||||||
c.words_per_row=4
|
|
||||||
debug.info(1, "Four bank, four way column mux with control logic")
|
|
||||||
a = sram(c, "sram3")
|
|
||||||
self.local_check(a, final_verification=True)
|
|
||||||
|
|
||||||
c.word_size=2
|
|
||||||
c.num_words=256
|
|
||||||
c.words_per_row=8
|
|
||||||
debug.info(1, "Four bank, eight way column mux with control logic")
|
|
||||||
a = sram.sram(c, "sram4")
|
|
||||||
self.local_check(a, final_verification=True)
|
|
||||||
|
|
||||||
globals.end_openram()
|
|
||||||
|
|
||||||
# run the test from the command line
|
|
||||||
if __name__ == "__main__":
|
|
||||||
(OPTS, args) = globals.parse_args()
|
|
||||||
del sys.argv[1:]
|
|
||||||
header(__file__, OPTS.tech_name)
|
|
||||||
unittest.main()
|
|
||||||
Loading…
Reference in New Issue